CN-121995827-A - Multi-project adaptation system for programmable logic device of aero-engine control system

CN121995827ACN 121995827 ACN121995827 ACN 121995827ACN-121995827-A

Abstract

The invention relates to the technical field of aeroengine control, and particularly discloses a multi-project adaptation system of a programmable logic device of an aeroengine control system, which comprises a programmable logic device, a CPU (Central processing Unit) and a hardware ID (identity) circuit, wherein the hardware ID circuit is used for outputting an ID signal and a check bit signal to the programmable logic device; the programmable logic device latches the ID signal and the check bit signal after the interactive confirmation is completed between the programmable logic device and the CPU, the programmable logic device checks the latched ID signal, the controller model is matched with the checked ID signal after the check is successful, the programmable logic device latches the matched controller model after the match is successful, and the adjustable parameters of the controller are adjusted according to the matched controller model. The invention enables a set of programmable logic device to be adaptable to a plurality of controller models with similar architecture and functions, and simultaneously can reduce redundant logic of the programmable logic device, and is simple, safe and reliable.

Inventors

ZHANG QIAN
YU ZHIJIE
ZHANG CHI
XU ZHILI
ZHANG BAICHUAN
Bian chuang

Assignees

中国航发控制系统研究所

Dates

Publication Date: 20260508
Application Date: 20260130

Claims (10)

1. A multi-project adaptation system of a programmable logic device of an aeroengine control system is characterized by comprising a programmable logic device, a CPU and a hardware ID circuit, wherein the CPU is connected with the programmable logic device through a communication bus, the hardware ID circuit is connected with the programmable logic device through a signal wire, the programmable logic device and the CPU can be subjected to interactive confirmation, the hardware ID circuit is used for outputting a current controller model ID signal and a check bit signal to the programmable logic device, After the programmable logic device and the CPU complete interactive confirmation, the programmable logic device latches the current controller model ID signal and the check bit signal; The programmable logic device checks the latched current controller model ID signal according to the latched check bit signal, and when the latched current controller model ID signal is successfully checked, the programmable logic device performs controller model matching on the checked current controller model ID signal; When the current controller model ID signal after successful verification is matched with the effective controller model, the programmable logic device latches the matched effective controller model, and adjusts the adjustable parameters of the controller according to the matched effective controller model.
2. The multi-project adaptive system for programmable logic devices of an aeroengine control system according to claim 1, wherein the hardware ID circuit is configured to provide the current controller model ID signal and the check bit signal, and the current controller model ID signal and the check bit signal are at a specific sequence of high-low levels formed by adjustable resistors or at a specific sequence of high-low levels output by pins of the CPU.
3. The aircraft engine control system programmable logic device multi-project adaptation system of claim 1, wherein the hardware ID circuit outputs the current controller model ID signal to the programmable logic device via an ID signal line, and wherein the hardware ID circuit outputs the check bit signal to the programmable logic device via a check bit signal line; The number of the ID signal lines is n, and if the number of the controller models to be adapted is M, 2 n should be not less than M.
4. The system of claim 1, wherein when the check bit signal does not match the current controller model ID signal, it indicates that the hardware ID circuit has a short circuit, a circuit break, and a signal source fault output.
5. The multiple project adaptation system of a programmable logic device of an aircraft engine control system according to claim 1, wherein the process of interactive validation between the programmable logic device and the CPU is as follows: A first successful loading identification register and a second successful loading identification register are arranged in the programmable logic device, and when the programmable logic device is successfully loaded and initialized, the programmable logic device sets a first successful loading identification in the first successful loading identification register to be effective; When the CPU reads that the first loading success identification is valid through the communication bus, the programmable logic device is considered to be initialized, and the programmable logic device can perform ID signal verification and matching flow at any time; at this time, the hardware ID circuit needs to output the current controller model ID signal and the check bit signal to the programmable logic device, and then the CPU writes a fixed value in the second loading success identification register through the communication bus, that is, sets the second loading success identification in the second loading success identification register to be valid; When the programmable logic device detects that the second loading success identification is valid, the programmable logic device completes the interactive confirmation with the CPU, and then the programmable logic device starts the process of ID signal verification and matching.
6. The multiple project adaptation system of a programmable logic device of an aircraft engine control system according to claim 5, wherein an identification completion status identification register, a verification error identification register and a matching error identification register are provided inside the programmable logic device; The identification completion state identifier in the identification completion state identifier register is used for representing whether the programmable logic device has been subjected to ID signal verification and matching, and the verification error identifier in the verification error identifier register is used for indicating whether the current controller model ID signal is matched with the check bit signal; when the initialization of the programmable logic device is completed, the initial values of the identification completion state identification, the verification error identification and the matching error identification are all invalid values.
7. The multi-project adaptation system for programmable logic devices of an aeroengine control system according to claim 6, wherein the process of checking and matching ID signals of the programmable logic devices is as follows: step 1, the programmable logic device latches the current controller model ID signal and the check bit signal; Step 2, the programmable logic device checks the latched current controller model ID signal according to the latched check bit signal, if the latched check bit signal is matched with the latched current controller model ID signal, the check of the latched current controller model ID signal is successful, step 3 is performed, if the latched check bit signal is not matched with the latched current controller model ID signal, the programmable logic device considers that the latched current controller model ID signal is not trusted, the programmable logic device sets the check error identification and the identification completion state identification to be valid, and maintains the initialization setting of the adjustable parameters of the controller, and the flow of checking and matching the ID signal is ended; Step 3, the programmable logic device performs controller model matching on the current controller model ID signal after successful verification, if the current controller model ID signal after successful verification is matched with an effective controller model, step 4 is performed, if the current controller model ID signal after successful verification is not matched with the effective controller model, the programmable logic device sets the matching error identification and the identification completion state identification to be effective, and maintains the initialization setting of the adjustable parameters of the controller, and the flow of checking and matching the ID signal is ended; and 4, latching the matched effective controller model by the programmable logic device, setting the identification completion state identification as effective, adjusting the adjustable parameters of the controller according to the matched effective controller model, and ending the ID signal checking and matching process.
8. The system of claim 7, wherein the CPU is capable of reading the ID verification and matching results and the controller adjustable parameters of the programmable logic device via the communication bus.
9. The multi-project adaptation system of the programmable logic device of the aeroengine control system according to claim 8, wherein the CPU judges whether the programmable logic device has completed the ID signal checking and matching process currently according to the read identification completion state identification; under a normal state, when the identification of the completion state is valid, checking the error identification and the matching error identification to be invalid, wherein the model of the matched effective controller in the programmable logic device is the same as the model of the controller set in the CPU; when the identification completion state identification is valid, if the verification error identification or the matching error identification is valid, and the current controller model ID signal and the check bit signal are output by the pins of the CPU, the CPU should check whether the current controller model ID signal and the check bit signal which are output by the CPU are wrong, if not, whether the pins and the connecting lines of the CPU are faulty or not should be considered, and corresponding alarm indication is carried out; When the identification completion state identification is valid, the verification error identification and the matching error identification are both invalid, but the model of the matched effective controller in the programmable logic device is different from the model of the controller set in the CPU or the adjustable parameters of the controller set in the programmable logic device are inconsistent with the preset value in the CPU, and the CPU carries out corresponding alarm indication.
10. The aircraft engine control system programmable logic device multi-project adaptation system of claim 7, wherein the programmable logic device is capable of protecting a current controller when the programmable logic device detects that the ID signal verification and matching is incomplete, the verification error identification is valid, or the matching error identification is valid, wherein in such a state the programmable logic device maintains the controller-adjustable parameter in an initialized setting.

Description

Multi-project adaptation system for programmable logic device of aero-engine control system Technical Field The invention relates to the technical field of aero-engine control, in particular to a multi-project adaptation system of a programmable logic device of an aero-engine control system. Background In the numerical control system of the aero-engine, the unified design of controllers with similar functions can reduce the design, test and management cost and improve the research and development efficiency. The programmable logic device is an important component in the numerical control system of the aeroengine, and the completion of the systematic work of the programmable logic device is an important ring of the systematic work of the controller. The system type numerical control system needs to have similar hardware architecture and functions, the programmable logic device identifies the type of the currently loaded controller by a certain method, and then preset logic selection is performed according to the identified type. The current adjustable parameters in the numerical control system are generally written by CPU software, the method is generally used for parameter adjustment of the same type of controller, and a set of highly reliable and highly safe programmable logic device logic selection mechanism suitable for a system type scheme is not formed. Therefore, the design of a logic selection mechanism of a programmable logic device suitable for multi-project system type is significant to the design of the current numerical control system type. Disclosure of Invention In order to solve the defects in the prior art, the invention provides a multi-project adaptation system for a programmable logic device of an aeroengine control system, so that one set of programmable logic device can adapt to a plurality of controller models with similar architecture and functions, and simultaneously, redundant logic of the programmable logic device can be reduced, and the system is simple, safe and reliable. As a first aspect of the present invention, there is provided an aircraft engine control system programmable logic device multi-project adaptation system, the aircraft engine control system programmable logic device multi-project adaptation system comprising a programmable logic device, a CPU and a hardware ID circuit, the CPU being connected to the programmable logic device via a communication bus, the hardware ID circuit being connected to the programmable logic device via a signal line, the programmable logic device and the CPU being capable of interactive verification, the hardware ID circuit being configured to output a current controller model ID signal and a parity signal to the programmable logic device, After the programmable logic device and the CPU complete interactive confirmation, the programmable logic device latches the current controller model ID signal and the check bit signal; The programmable logic device checks the latched current controller model ID signal according to the latched check bit signal, and when the latched current controller model ID signal is successfully checked, the programmable logic device performs controller model matching on the checked current controller model ID signal; When the current controller model ID signal after successful verification is matched with the effective controller model, the programmable logic device latches the matched effective controller model, and adjusts the adjustable parameters of the controller according to the matched effective controller model. The hardware ID circuit is used for providing the current controller model ID signal and the check bit signal, wherein the current controller model ID signal and the check bit signal are of specific sequence high-low level formed by adjustable resistors or of specific sequence high-low level output by pins of the CPU. Further, the hardware ID circuit outputs the ID signal of the current controller model to the programmable logic device through an ID signal line, and the hardware ID circuit outputs the check bit signal to the programmable logic device through a check bit signal line; The number of the ID signal lines is n, and if the number of the controller models to be adapted is M, 2 n should be not less than M. Further, when the check bit signal is not matched with the current controller model ID signal, the condition that the hardware ID circuit is short-circuited, broken and signal source is output by mistake is indicated. Further, the process of performing interactive confirmation between the programmable logic device and the CPU is as follows: A first successful loading identification register and a second successful loading identification register are arranged in the programmable logic device, and when the programmable logic device is successfully loaded and initialized, the programmable logic device sets a first successful loading identification in the first successful loading identification