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CN-121995990-A - Temperature control and monitoring method for memory chip FT test process

CN121995990ACN 121995990 ACN121995990 ACN 121995990ACN-121995990-A

Abstract

The invention belongs to the field of semiconductor function test, and particularly relates to a temperature control and monitoring method for a memory chip FT test process. The method comprises the steps of establishing an electrothermal dual-domain coupling characteristic model to record the mapping relation of power consumption, thermal resistance and internal junction temperature, sampling transient electrical parameters during testing of a storage chip in real time and calculating real-time power consumption, resolving dynamic junction temperature in real time by utilizing a virtual mapping algorithm to construct a digital mapping entity for storing the thermal state of the chip, identifying thermal resistance network parameters on line by utilizing a self-adaptive filtering algorithm by comparing the dynamic junction temperature with the actual measured shell temperature, predicting junction temperature change according to a test item jump signal and generating a feedforward compensation instruction, and finally driving a fluid executing mechanism to adjust the mixing proportion of cold and hot media by taking the dynamic junction temperature as a main feedback quantity. According to the invention, through the active prediction control of the electric heating coordination, the heat transfer hysteresis influence is eliminated, the accurate locking of the junction temperature in the memory chip is realized, and the stability and the production efficiency of the test result are improved.

Inventors

  • JIANG WEN
  • Cai Liangyong
  • YANG DONGYAN
  • ZHU HOUQUAN

Assignees

  • 深圳市舟鸿半导体科技有限公司

Dates

Publication Date
20260508
Application Date
20260410

Claims (10)

  1. 1. The temperature control and monitoring method for the FT testing process of the memory chip is characterized by comprising the following steps of: Step 1, establishing an electrothermal dual-domain coupling characteristic model, and obtaining and recording mapping relations among power consumption, structural thermal resistance and internal junction temperature of a storage chip in different working modes by calibrating thermal characteristics of the storage chip to form a multidimensional characteristic library; Step2, acquiring electrical operation parameters in real time, and detecting and recording transient working current and transient working voltage of the memory chip when the memory chip operates a test vector through a high-speed synchronous sampling unit in the test process of the memory chip; step 3, performing electric heating virtual mapping calculation, calculating real-time power consumption by using the collected transient working current and the transient working voltage, calling the mapping relation by combining preset calculation logic, and resolving the dynamic junction temperature in the memory chip in real time by a virtual mapping algorithm; Step 4, implementing on-line identification of the thermal resistance network, comparing the calculated dynamic junction temperature with the chip shell temperature acquired by the physical sensor, and dynamically identifying real-time thermal resistance network parameters from the chip junction to the test environment by utilizing a self-adaptive filtering algorithm; Step 5, generating a feedforward compensation control instruction, receiving a test item jump signal issued by a test machine in real time, acquiring a time node with power consumption suddenly changed in advance, calculating the variation of a pre-judging junction temperature according to the electric heating virtual mapping, and generating a compensatory fluid flow regulating instruction; And 6, executing closed loop feedback adjustment, taking the dynamic junction temperature as a main feedback quantity, taking the chip shell temperature as an auxiliary feedback quantity, generating a control signal through a regulator, and driving a fluid executing mechanism to adjust the mixing proportion of the medium so as to lock the junction temperature in the memory chip.
  2. 2. The method for controlling and monitoring the temperature of the memory chip FT testing process according to claim 1, wherein the process of establishing the electrothermal dual-domain coupling feature model in step 1 comprises establishing a fine thermal model of the memory chip by using thermal simulation software, and gridding a silicon wafer, a lead frame, a plastic packaging resin, a solder ball array, a matched test seat and a test carrier plate inside the memory chip; Extracting the corresponding heat conductivity, specific heat capacity, thermal expansion coefficient and density parameters of each packaging material from a material attribute library, and setting a functional relation of the parameters along with the temperature change; Analyzing thermal diffusion paths of the memory chip under different packaging materials and pin arrangements, extracting physical positions of each power supply pin and each ground pin, calculating parasitic resistance heating of each pin in a signal transmission process, and loading the parasitic resistance heating serving as a local heat source into the fine thermal model; simulating the contact condition of the test base and the surface of the memory chip under different pressure gradients, establishing a contact thermal resistance model, and obtaining a negative correlation mapping curve between the contact thermal resistance and the mechanical pressure; Applying a stepping power load to a sample chip in an experimental environment, recording the indication values of the chip shell temperature and an internal temperature sensor at different environmental temperature points, and obtaining a nonlinear compensation coefficient of thermal resistance along with temperature change; and fusing the simulation data of the fine thermal model with experimental calibration data to form a characteristic table which takes working voltage, working current and ambient temperature as input variables and junction temperature as output variables, and storing the characteristic table in a nonvolatile storage unit.
  3. 3. The method for controlling and monitoring the temperature of the memory chip FT testing process according to claim 2, wherein the process of acquiring the electrical operation parameters in real time in the step 2 comprises the steps of connecting a current monitoring circuit in series in a power supply channel of the memory chip, wherein the current monitoring circuit adopts a Hall effect sensor or a precision sampling resistor to be matched with an instrument amplifier to acquire a current waveform of a power supply pin of the memory chip; monitoring the input voltage of the memory chip through a voltage comparator to obtain the ripple variation of the voltage; The sampling frequency of the high-speed synchronous sampling unit is kept synchronous with the clock period of the test machine, so that the electrical characteristics corresponding to each test vector of the memory chip operation are ensured to be completely captured; The sampling control logic and the trigger signal of the test machine keep the synchronization of the hardware level, and each time a start trigger pulse is initiated under the test machine, the high-speed synchronous sampling unit starts a sampling mode; The transient working current and the transient working voltage obtained by sampling are cached in a random access memory, and high-frequency impulse noise is filtered through first-order lag filtering before entering calculation logic.
  4. 4. The method for controlling and monitoring the temperature of the memory chip FT testing process according to claim 3, wherein the process of executing the electrothermal virtual mapping calculation in step 3 includes performing product operation on the transient operating current and the transient operating voltage acquired in real time to obtain the total transient power consumption of the memory chip in the current test period; Analyzing task status words from the test machine, and identifying a logic operation mode in which the memory chip is currently located, wherein the logic operation mode comprises a standby mode, a continuous reading operation mode, a page programming operation mode or a whole-chip erasing mode; According to the identified logic operation mode, a corresponding thermal resistance reference value is called from the multidimensional feature library; using the product of the transient total power consumption and the thermal resistance reference value as a temperature increment, and superposing the temperature increment on the reference temperature measured by the physical sensor to obtain an initial estimated value of the dynamic junction temperature; And carrying out time domain smoothing on the initial estimated value of the dynamic junction temperature by using a heat capacity correction factor to compensate phase shift generated by thermal inertia of the packaging material, wherein the phase shift compensation process is carried out by calculating the difference value between the initial estimated value at the current moment and the dynamic junction temperature value at the previous moment and multiplying the difference value by an attenuation coefficient related to the packaging thermal time constant.
  5. 5. The method for controlling and monitoring the temperature of the memory chip FT test process according to claim 4, wherein the virtual mapping algorithm in step 3 further comprises a compensation logic for the internal multi-part heating non-uniformity of the memory chip, and dividing the memory chip into a memory array area, a logic control area and a peripheral interface area according to the internal layout design of the memory chip; According to the activation degree of different test vectors to different functional areas, different weight coefficients are distributed; When parallel reading test is carried out, the weight coefficient of the memory array area is improved, and when serial interface calibration test is carried out, the weight coefficient of the peripheral interface area is improved; And calculating the local temperature distribution of each functional area, and obtaining an equivalent junction temperature value through a weighted average algorithm.
  6. 6. The method for controlling and monitoring the temperature of the memory chip FT testing process according to claim 5, wherein the process of implementing the on-line identification of the thermal resistance network in step 4 comprises constructing a thermal resistance observer based on a state space equation, taking the dynamic junction temperature as a state variable and the chip shell temperature as an observation variable; performing a prediction step and an update step within a sampling period using a kalman filter algorithm; In the predicting step, a thermal resistance predicted value and a covariance matrix predicted value at the current moment are calculated by using a thermal resistance state value and a heat transfer state transition matrix at the previous moment; In the updating step, the physical sensor is used for collecting an actual measurement value of the chip shell temperature, and an observation residual error between the actual measurement value and the predicted shell temperature is calculated; calculating a gain coefficient according to the state prediction covariance and the observation noise covariance, weighting the observation residual error by using the gain coefficient, and correcting the thermal resistance prediction value; and the identification process identifies thermal resistance drift caused by aging of the metal probe of the test seat, fluctuation of contact pressure or change of humidity of the test environment, and feeds back the corrected thermal resistance network parameters to the calculation process of the step 3.
  7. 7. The method for controlling and monitoring the temperature of the memory chip FT test process according to claim 6, wherein the step 5 of generating the feedforward compensation control command includes the steps of the test machine sending a pre-trigger pulse signal to the temperature control system at a predetermined clock period before executing the jump of the high power consumption test item; After the temperature control system analyzes the pre-trigger pulse signal, extracting the expected power consumption level of the next stage from the test vector sequence; calculating a difference value between the expected power consumption level and the current power consumption level, and calculating a junction temperature fluctuation amplitude caused by the difference value by combining the electric heating virtual mapping; deducing the compensation flow required by the fluid actuating mechanism by utilizing the junction temperature fluctuation amplitude caused by the difference value and combining an inversion algorithm of a heat conduction model; and adjusting the opening degree of the proportional valve in advance, and counteracting the transient change of the heating value of the memory chip through advanced control.
  8. 8. The method for controlling and monitoring the temperature of the memory chip FT test process according to claim 7, wherein the process of performing closed-loop feedback adjustment in step 6 comprises constructing a dual-loop control architecture, wherein the inner loop is a fluid flow control loop and the outer loop is a temperature compensation control loop; The proportional coefficient, the integral time constant and the differential time constant of the regulator carry out dynamic gain scheduling according to the real-time thermal resistance network parameters which are identified and output by the thermal resistance network on line; when the dynamic junction temperature deviates from a preset target value, the regulator of the outer ring generates a correction signal and is overlapped to the input end of the regulator of the inner ring; And the mixing proportion of the low-temperature fluid and the high-temperature fluid is adjusted through the fluid executing mechanism, so that the fluctuation range of the junction temperature in the memory chip in the whole testing process is ensured to be within a preset threshold value.
  9. 9. The method for controlling and monitoring the temperature of the memory chip FT testing process of claim 8 wherein the fluid actuator includes a circulation pump, a heating unit, a refrigerating unit, a three-way proportional mixing valve, a micro-channel heat exchanger, and a radiator fan; the circulating pump keeps constant-current circulation of the test medium in a closed circuit pipeline, and the heating unit and the refrigerating unit respectively maintain the test medium in a preset high-temperature state and a preset low-temperature state; The three-way proportional mixing valve distributes the proportion of cold and hot media entering the microchannel heat exchanger according to the control signal; the micro-channel heat exchanger is in contact with the test seat, and the temperature of the memory chip is raised or lowered in a heat conduction mode; when the memory chip is predicted to enter a high power consumption mode, the pulse width modulation duty ratio of the cooling fan is synchronously increased, and the heat convection intensity of the surface of the test interface unit is enhanced.
  10. 10. The method for controlling and monitoring the temperature of the memory chip FT testing process according to claim 9, further comprising continuously monitoring the air flow rate, the ambient humidity and the test seat contact pressure in the test cavity using a multi-physical quantity sensing matrix; When the ambient humidity is monitored to exceed a preset range, starting a nitrogen purging device, and forming a dry inert gas protection layer in a test area; When the contact pressure of the test seat is monitored to be lower than a preset threshold value or the pressure unbalance exists, an early warning signal is sent out and the feedforward compensation control instruction is interrupted; Before the test task is finished and the chip pops up, starting a temperature return logic, and driving the fluid executing mechanism to raise the temperature to a normal temperature state; and the electrothermal dual-domain coupling characteristic model is subjected to self-learning updating regularly, and by collecting junction temperature fluctuation data and electrical parameter characteristics, model deviation is identified by utilizing a machine learning algorithm, and parameters in the multidimensional characteristic library are corrected.

Description

Temperature control and monitoring method for memory chip FT test process Technical Field The invention belongs to the field of semiconductor function test, and particularly relates to a temperature control and monitoring method for a memory chip FT test process. Background With the rapid development of large-scale integrated circuit technology, memory chips are increasingly used in the fields of high-performance computing, artificial intelligence and the like. The final test is used as a key link in the semiconductor manufacturing process, and potential failure products can be screened by performing full-function electrical performance verification on the chip in a controlled temperature environment. The high-precision temperature control is not only the basis for simulating a real application scene, but also the core premise for ensuring the time sequence accuracy and logic accuracy of the memory chip under a severe working condition. Temperature control and monitoring of the final test process of the memory chip involves closed loop thermal management of the test cavity and the chip itself. The technology generally utilizes external temperature control equipment to generate constant heat flow or refrigerant medium, and acts on a chip to be tested in a heat conduction mode, so that the junction temperature inside the chip is locked at a target test point in real time. In order to grasp the test state, the system needs to integrate a sensor to acquire temperature data, and regulate a temperature control executing mechanism by combining instructions issued by a test machine table, so as to provide stable thermal environment support for the high-power consumption memory chip. When the prior art is used for testing a high-speed memory chip, the problem of mismatch between macroscopic environment temperature control and microscopic chip junction temperature is generally faced, so that the heat transfer is obviously delayed, and the transient heat change of the chip caused by severe fluctuation of power consumption is difficult to respond in real time. Meanwhile, the temperature control and monitoring paths are often in a functional fracture state, and a high-bandwidth closed loop feedback mechanism is lacked, so that the system has lower robustness when facing complex working conditions such as aging of a test interface or contact thermal resistance drift. The traditional scheme can not establish the deep correlation between the electrical characteristics of the chip and the heating mechanism, and can not pre-judge and compensate the nonlinear thermal stress caused by the switching of the test vectors, so that the junction temperature frequently oscillates and the yield loss is induced. Disclosure of Invention The invention aims to provide a temperature control and monitoring method for a memory chip FT test process, which can solve the problems in the background technology. In order to achieve the purpose, the technical scheme adopted by the invention is that the temperature control and monitoring method for the FT testing process of the memory chip comprises the following specific steps: step 1, establishing an electrothermal dual-domain coupling characteristic model, and obtaining and recording multi-dimensional mapping relations among transient power consumption, structural thermal resistance and internal junction temperature of a memory chip in different working modes by carrying out pre-thermal characteristic calibration on the memory chips of different types to form a multi-dimensional characteristic library; Step 2, acquiring electrical operation parameters in real time, and detecting and recording transient working current and transient working voltage of the memory chip when a specific test vector is operated by the memory chip in real time through a high-speed synchronous sampling unit in the process of carrying out final test on the memory chip; Step 3, executing electric heating virtual mapping calculation, utilizing the collected transient working current and transient working voltage, combining preset calculation logic to obtain real-time power consumption, calling a preset multidimensional mapping relation, resolving the dynamic junction temperature in the memory chip in real time through an embedded virtual mapping algorithm, and constructing a digital mapping entity of the thermal state of the memory chip; Step 4, implementing on-line identification of the thermal resistance network, comparing the calculated dynamic junction temperature with the temperature of the chip shell acquired by the physical sensor arranged at the bottom of the test seat in real time, and dynamically identifying real-time thermal resistance network parameters from the chip junction to the test environment by utilizing an adaptive filtering algorithm; Step 5, generating a feedforward compensation control instruction, receiving a test item jump signal issued by a test machine in real time, acquiring a time node with pow