CN-121996008-A - Voltage output circuit and power management chip

Abstract

The invention provides a voltage output circuit and a power management chip. In the voltage output circuit, the first output module is of a FVF type LDO structure and comprises a bias ring and a first quick response ring, wherein the second end voltage of the first power tube is a first output voltage, the second output module comprises a second quick response ring, the gate end of the second source following transistor is coupled with the output end of the operational amplifier in the first output module, the second end voltage of the second power tube is a second output voltage, the first output voltage and the second output voltage are both provided with characteristics of being adjusted along with load changes, abnormal electric leakage does not occur when the output voltage is switched, the voltage output part can be switched without a level conversion circuit, and the occupied area of the voltage output part in a chip is smaller. The power management chip comprises the voltage output circuit.

Inventors

• LI CHEN
• TIAN HUAN
• WAN YUHANG

Assignees

• 兆易创新科技集团股份有限公司

Dates

Publication Date

20260508

Application Date

20241108

Claims (10)

1. 1. A voltage output circuit, comprising: A first output module including a bias ring including an operational amplifier and a first source follower transistor, and a first fast response ring including the first source follower transistor and a first power transistor, wherein the gate terminal of the first source follower transistor is coupled to the output terminal of the operational amplifier, the first terminal of the first power transistor is coupled to the circuit input voltage and the second terminal is coupled to the first terminal of the first source follower transistor, the second terminal voltage of the first power transistor is a first output voltage, and the two input terminals of the operational amplifier are respectively coupled to the feedback voltage and a reference voltage of the first output voltage The second output module comprises a second quick response loop comprising a second source following transistor and a second power tube, wherein the gate end of the second source following transistor is coupled with the output end of the operational amplifier, the first end of the second power tube is coupled with the input voltage of the circuit, the second end of the second power tube is coupled with the first end of the second source following transistor, and the second end voltage of the second power tube is a second output voltage.
2. 2. The voltage output circuit of claim 1 wherein the first fast response loop comprises a first current mirror unit for copying a second terminal current of the first source follower transistor to the second current mirror unit, and a second current mirror unit for copying a current copied from the first current mirror unit to a gate terminal of the first power transistor.
3. 3. The voltage output circuit of claim 1 wherein the first fast response loop comprises a first current source coupled between a gate terminal of the first power tube and ground.
4. 4. The voltage output circuit of claim 1 wherein the second fast response loop comprises a third current mirror unit for copying a second terminal current of the second source follower transistor to a fourth current mirror unit for copying a current copied from the third current mirror unit to a gate terminal of the second power transistor.
5. 5. The voltage output circuit of claim 1 wherein the second fast response loop comprises a second current source coupled between a gate terminal of the second power tube and ground.
6. 6. The voltage output circuit according to any one of claims 1 to 5, further comprising: The third output module comprises a first transistor, a second transistor, a third voltage source and a fourth voltage source, wherein a first end of the first transistor is coupled with the first output voltage, a gate end of the first transistor is coupled with the second end of the first transistor, the third voltage source is coupled between the circuit input voltage and the second end of the first transistor, a second end of the second transistor and the second end of the third transistor are coupled with the circuit input voltage, the gate end of the third transistor is coupled with the gate end of the first transistor, the first end voltage of the third transistor is a third output voltage, and the fourth voltage source is coupled between the third output voltage and ground.
7. 7. The voltage output circuit of claim 6 wherein the third output voltage is used to provide power to a logic circuit.
8. 8. A voltage output circuit as claimed in any one of claims 1 to 5 wherein the first output voltage and the second output voltage are used to provide power for different voltage domains.
9. 9. A power management chip comprising a voltage output circuit as claimed in any one of claims 1 to 8.
10. 10. The power management chip of claim 9, wherein the power management chip is configured to provide power for different voltage domains.

Description

Voltage output circuit and power management chip Technical Field The present invention relates to the field of circuit technologies, and in particular, to a voltage output circuit and a power management chip. Background With the development of technology, the integration level of a chip is higher and higher, more than one power supply voltage is needed by different digital or analog circuit modules in the chip, a level conversion (LEVEL SHIFT) circuit is needed to switch signal voltage domains in the operation process, and the larger the scale of the chip, the more signals need to be switched, so that the larger the area occupied by the level conversion circuit is. Compared with a DC-DC converter, the LDO (low dropout regulator) occupies smaller area and has higher linearity, and is more suitable for occasions with higher requirements on occupied area and linearity, such as portable terminal equipment. In the prior art, when different voltage source outputs are generated by using LDOs, multiplexing is usually adopted to realize the grid end of the LDO power tube, but some voltage sources have slight differences in voltage due to different loads, so that the switching needs to be performed by a level switching circuit, otherwise, abnormal leakage problems exist, and the overall occupied area is larger. Disclosure of Invention In order to avoid abnormal electric leakage so as to reduce the occupied area of a voltage output part in a chip while generating different voltage sources, the invention provides a voltage output circuit and a power management chip. In one aspect, the present invention provides a voltage output circuit comprising: A first output module including a bias ring including an operational amplifier and a first source follower transistor, and a first fast response ring including the first source follower transistor and a first power transistor, wherein the gate terminal of the first source follower transistor is coupled to the output terminal of the operational amplifier, the first terminal of the first power transistor is coupled to the circuit input voltage and the second terminal is coupled to the first terminal of the first source follower transistor, the second terminal voltage of the first power transistor is a first output voltage, and the two input terminals of the operational amplifier are respectively coupled to the feedback voltage and a reference voltage of the first output voltage The second output module comprises a second quick response loop comprising a second source following transistor and a second power tube, wherein the gate end of the second source following transistor is coupled with the output end of the operational amplifier, the first end of the second power tube is coupled with the input voltage of the circuit, the second end of the second power tube is coupled with the first end of the second source following transistor, and the second end voltage of the second power tube is a second output voltage. Optionally, the first fast response loop includes a first current mirror unit and a second current mirror unit, wherein the first current mirror unit is configured to copy a second end current of the first source follower transistor to the second current mirror unit, and the second current mirror unit is configured to copy a current copied from the first current mirror unit to a gate end of the first power tube. Optionally, the first fast response loop includes a first current source coupled between a gate terminal of the first power tube and ground. Optionally, the second fast response loop includes a third current mirror unit and a fourth current mirror unit, wherein the third current mirror unit is configured to copy the second terminal current of the second source follower transistor to the fourth current mirror unit, and the fourth current mirror unit is configured to copy the current copied from the third current mirror unit to the gate terminal of the second power tube. Optionally, the second fast response loop includes a second current source coupled between the gate terminal of the second power tube and ground. Optionally, the voltage output circuit further comprises: the third output module comprises a first transistor, a second transistor, a third voltage source and a fourth voltage source, wherein a first end of the first transistor is coupled with the first output voltage, a gate end of the first transistor is coupled with the second end of the first transistor, the third voltage source is coupled between the circuit input voltage and the second end of the first transistor, a second end of the second transistor and the second end of the third transistor are coupled with the circuit input voltage, the gate end of the third transistor is coupled with the gate end of the first transistor, the first end voltage of the third transistor is a third output voltage, and the fourth voltage source is coupled between the third output voltage and ground. Optionally, the t