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CN-121996014-A - Low-temperature drift sectional compensation band gap reference circuit

CN121996014ACN 121996014 ACN121996014 ACN 121996014ACN-121996014-A

Abstract

The invention relates to a low-temperature drift sectional compensation band gap reference circuit, which relates to the field of analog integrated circuit design. According to the technical scheme, by designing the linear piecewise compensation circuit, two sections of linear compensation currents adaptive to temperature can be output and accurately overlapped on the opening downward parabolic temperature characteristic voltage output by the first-order compensation band gap reference circuit. The two sections of compensation currents respectively correspond to the low temperature region and the high temperature region to realize targeted compensation, the middle temperature region has no additional compensation interference, and the influence caused by high-order nonlinear temperature distortion is effectively counteracted through the accurate adaptation and characteristic superposition of the temperature region. Compared with the traditional first-order compensation scheme, the invention can obviously inhibit the temperature drift of the band-gap reference voltage without a complex topological structure, is suitable for wide-temperature-range application scenes, and provides stable references for devices such as a subsequent low-dropout linear voltage regulator, a high-precision analog-to-digital converter and the like.

Inventors

  • HUANG CAN
  • YU YUNFENG

Assignees

  • 南京中科微电子有限公司

Dates

Publication Date
20260508
Application Date
20260126

Claims (10)

  1. 1. The low-temperature drift sectional compensation band gap reference circuit is characterized by comprising a starting circuit (1), a first-order compensation band gap reference circuit (2), a sectional compensation circuit (3) and a bias circuit (4); the starting circuit (1) is electrically connected with the first-order compensation band gap reference circuit (2), and the starting circuit (1) is used for injecting current into the first-order compensation band gap reference circuit (2) when power is applied so as to enable the first-order compensation band gap reference circuit to deviate from a degeneracy point; the first-order compensation band-gap reference circuit (2) is electrically connected with the segment compensation circuit (3), and the first-order compensation band-gap reference circuit (2) is used for providing a band-gap reference voltage for eliminating a first-order temperature coefficient and providing a connection node for the segment compensation circuit (3); The piecewise compensation circuit (3) is electrically connected with the bias circuit (4), and the piecewise compensation circuit (3) is used for providing linear piecewise compensation current for the band gap reference voltage; the bias circuit (4) is electrically connected with the first-order compensation band gap reference circuit (2) and the segmentation compensation circuit (3) respectively, and provides stable bias voltage for the first-order compensation band gap reference circuit and the segmentation compensation circuit.
  2. 2. The low temperature drift sectional compensation bandgap reference circuit of claim 1, wherein said start-up circuit (1) comprises a first PMOS transistor MP1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a first resistor R1; One end of the first resistor R1 is connected with a power supply voltage Vref, and the other end of the first resistor R1 is connected with the drain electrode of the first NMOS tube MN 1; The grid electrode of the first NMOS tube MN1 and the grid electrode of the second NMOS tube MN2 are connected with the drain electrode of the first NMOS tube MN1 in a sharing way; The grid electrode of the first PMOS tube MP1 is connected with a control signal VOEN, the source electrode of the first PMOS tube MP1 is connected with a power supply voltage Vref, and the drain electrode of the first PMOS tube MP1 is connected with the drain electrode of the second NMOS tube MN 2; The source electrode of the first NMOS tube MN1 is commonly connected with the drain electrode of the third NMOS tube MN3 and the grid electrode of the third NMOS tube MN 3; the source electrode of the third NMOS tube MN3 is commonly connected with the drain electrode of the fourth NMOS tube MN4 and the grid electrode of the fourth NMOS tube MN 4; the source electrode of the fourth NMOS tube MN4 is commonly connected with the drain electrode of the fifth NMOS tube MN5 and the grid electrode of the fifth NMOS tube MN 5; the source electrode of the fifth NMOS tube MN5 is connected with the drain electrode of the sixth NMOS tube MN6, and the grid electrode of the sixth NMOS tube MN6 is connected with a control signal VOE; the source electrode of the second NMOS tube MN2 is connected with the first-order compensation band gap reference circuit (2).
  3. 3. The low temperature drift sectional compensation bandgap reference circuit of claim 1, wherein said first order compensation bandgap reference circuit (2) comprises a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a first transistor QN1, a second transistor QN2, a third transistor QN3, a fourth transistor QN4, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9; one end of the second resistor R2 is connected with the power voltage Vref, and the other end of the second resistor R2 is simultaneously connected with the source electrode of the second PMOS tube MP2, the source electrode of the third PMOS tube MP3 and the source electrode of the fourth PMOS tube MP 4; The grid electrode of the fourth PMOS tube MP4 is connected with a control signal OEN; the grid electrode of the second PMOS tube MP2 and the grid electrode of the third PMOS tube MP3 are connected with the drain electrode of the second PMOS tube MP2 in common; the drain electrode of the second PMOS transistor MP2 is connected to the drain electrode of the seventh NMOS transistor MN7, and the drain electrode of the third PMOS transistor MP3 is commonly connected to the drain electrode of the eighth NMOS transistor MN8, one end of the third resistor R3, and the gate electrode of the tenth NMOS transistor MN 10; the other end of the third resistor R3 is commonly connected with the grid electrode of the seventh NMOS tube MN7 and the grid electrode of the eighth NMOS tube MN 8; the source electrode of the seventh NMOS transistor MN7 is connected with the collector electrode of the first triode QN1, the source electrode of the eighth NMOS transistor MN8 is connected with the collector electrode of the second triode QN2, and the emitter electrodes of the first triode QN1 and the second triode QN2 are grounded; the base electrode of the first triode QN1 and the base electrode of the second triode QN2 are connected with the collector electrode of the fourth triode QN 4; The drain electrode of the tenth NMOS tube MN10 is connected with the drain electrode of the fourth PMOS tube MP4, and the source electrode of the tenth NMOS tube MN10 is simultaneously connected with one end of the fifth resistor R5 and the source electrode and the drain electrode of the eleventh NMOS tube MN 11; the grid electrode of the eleventh NMOS tube MN11 is simultaneously connected with the base electrode of the third triode QN3 and one end of the fourth resistor R4 in a sharing way; The other end of the fourth resistor R4 is simultaneously connected with the collector electrode of the third triode QN3 and the base electrode of the fourth triode QN4 in a sharing way; the fifth resistor R5, the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 are sequentially connected in series, two ends of the sixth resistor R6 are connected with the segmentation compensation circuit (3), and the other end of the eighth resistor R8 is connected with the collector electrode of the fourth triode QN 4; The emitter of the third triode QN3 and the emitter of the fourth triode QN4 are connected with one end of the ninth resistor R9, and the other end of the ninth resistor R9 is grounded.
  4. 4. The low temperature drift sectional compensation bandgap reference circuit of claim 1, wherein said sectional compensation circuit (3) comprises a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, a sixteenth NMOS transistor MN16, a seventeenth NMOS transistor MN17, an eighteenth NMOS transistor MN18, a nineteenth NMOS transistor MN19, a twenty-first NMOS transistor MN21, a twenty-second NMOS transistor MN22, a twenty-third NMOS transistor MN23, a twenty-fourth NMOS transistor MN24, a twenty-fifth NMOS transistor MN25, a tenth resistor R10, and an eleventh resistor R11; The source electrode of the fifth PMOS tube MP5 is connected with the bias circuit (4), the grid electrode of the fifth PMOS tube MP5 is connected with a control signal OEN, and the drain electrode of the fifth PMOS tube MP5 is simultaneously connected with one end of the tenth resistor R10 and one end of the eleventh resistor R11; The other end of the tenth resistor R10 is connected with the source electrode of the sixth PMOS tube MP6, the grid electrode of the sixth PMOS tube MP6 is connected with a reference voltage Vref, and the drain electrode of the sixth PMOS tube MP6 is simultaneously connected with the drain electrode of the fourteenth NMOS tube MN14 and the drain electrode of the twenty-fourth NMOS tube MN 24; the grid electrode of the fourteenth NMOS tube MN14 and the grid electrode of the thirteenth NMOS tube MN13 are connected with the drain electrode of the fourteenth NMOS tube MN14 in a sharing way; the other end of the eleventh resistor R11 is connected with the source electrode of the seventh PMOS tube MP7, the grid electrode of the seventh PMOS tube MP7 is connected with the bias circuit (4), and the drain electrode of the seventh PMOS tube MP7 is simultaneously connected with the drain electrode of the fifteenth NMOS tube MN15 and the drain electrode of the sixteenth NMOS tube MN 16; the grid electrode of the fifteenth NMOS tube MN15 and the grid electrode of the twelfth NMOS tube MN12 are connected with the drain electrode of the fifteenth NMOS tube MN15 in a sharing mode; The seventeenth NMOS transistor MN17, the eighteenth NMOS transistor MN18, and the nineteenth NMOS transistor MN19 are sequentially connected in series, the source of the nineteenth NMOS transistor MN19 is grounded, and the drain of the seventeenth NMOS transistor MN17 and the drain of the sixteenth NMOS transistor MN16 are commonly connected; The twenty-first NMOS tube MN21, the twenty-second NMOS tube MN22 and the twenty-third NMOS tube MN23 are sequentially connected in series, the source electrode of the twenty-third NMOS tube MN23 is grounded, and the drain electrode of the twenty-first NMOS tube MN21 and the drain electrode of the twenty-fourth NMOS tube MN24 are connected together; The gates of the sixteenth NMOS transistor MN16, the seventeenth NMOS transistor MN17, the eighteenth NMOS transistor MN18, the nineteenth NMOS transistor MN19, the twenty first NMOS transistor MN21, the twenty second NMOS transistor MN22, the twenty third NMOS transistor MN23, the twenty fourth NMOS transistor MN24, and the twenty fifth NMOS transistor MN25 are all commonly connected to the bias circuit (4).
  5. 5. The low temperature drift sectional compensation bandgap reference circuit of claim 1, wherein said bias circuit (4) comprises an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a twenty-sixth NMOS transistor MN26, a twenty-seventh NMOS transistor MN27, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifth triode QN5 and a sixth triode QN6; The sources of the eighth PMOS transistor MP8, the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are all connected to the power supply VDD, and the gates of the eighth PMOS transistor MP8, the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are all commonly connected to the drain of the eighth PMOS transistor MP 8; the drain electrode of the eighth PMOS tube MP8 is connected with the source electrode of the eleventh PMOS tube MP 11; The grid electrode of the eleventh PMOS tube MP11, the grid electrode of the twelfth PMOS tube MP12 and the grid electrode of the thirteenth PMOS tube MP13 are all connected with the drain electrode of the eleventh PMOS tube MP11 in common; The drain electrode of the eleventh PMOS transistor MP11 is connected to the drain electrode of the sixteenth NMOS transistor MN16, and the source electrode of the sixteenth NMOS transistor MN16 is simultaneously connected to one end of the twelfth resistor R12, one end of the thirteenth resistor R13, and one end of the fourteenth resistor R14, and the other end of the twelfth resistor R12, the other end of the thirteenth resistor R13, and the other end of the fourteenth resistor R14 are all grounded; The drain electrode of the ninth PMOS tube MP9 is connected with the source electrode of the twelfth PMOS tube MP12, and the drain electrode of the twelfth PMOS tube MP12 is connected with the collector electrode of the fifth triode QN 5; the base electrode of the fifth triode QN5 is commonly connected with the collector electrode of the fifth triode QN5, and the emitter electrode of the fifth triode QN5 is connected with the collector electrode of the sixth triode QN 6; The base electrode of the sixth triode QN6 is commonly connected with the collector electrode of the sixth triode QN6, and the emitter electrode of the sixth triode QN6 is grounded; the drain electrode of the tenth PMOS tube MP10 is connected with the source electrode of the thirteenth PMOS tube MP13, and the drain electrode of the thirteenth PMOS tube MP13 is connected with the segment compensation circuit (3); The drain electrode of the twenty-sixth NMOS tube MN26 is connected with the source electrode of the twenty-seventh NMOS tube MN27, and the drain electrode of the twenty-seventh NMOS tube MN27 is connected with the segmentation compensation circuit (3).
  6. 6. The low temperature drift sectional compensation bandgap reference circuit of claim 2, wherein said first NMOS transistor MN1, said third NMOS transistor MN3, said fourth NMOS transistor MN4, said fifth NMOS transistor MN5 in said start-up circuit (1) are the same size; The width-to-length ratio of the first NMOS transistor MN1 is the same as that of the second NMOS transistor MN2, and the first NMOS transistor MN1 and the second NMOS transistor MN2 form a current mirror structure.
  7. 7. A low temperature drift sectional compensation bandgap reference circuit according to claim 3, characterized in that the ratio of the emitter areas of said third transistor QN3 and said fourth transistor QN4 in said first order compensation bandgap reference circuit (2) is 1:8; The second PMOS transistor MP2, the third PMOS transistor MP3, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, and the third resistor R3 form an operational amplifier; And the ninth NMOS tube MN9 is matched with the third resistor R3 to realize zero pole compensation of the operational amplifier.
  8. 8. The low temperature drift sectional compensation bandgap reference circuit of claim 4, wherein said sixth PMOS transistor MP6 and said seventh PMOS transistor MP7 in said sectional compensation circuit (3) both operate in a subthreshold region; The sixteenth NMOS transistor MN16, the seventeenth NMOS transistor MN17, the eighteenth NMOS transistor MN18, the nineteenth NMOS transistor MN19, the twenty fourth NMOS transistor MN24, the twenty first NMOS transistor MN21, the twenty second NMOS transistor MN22, the twenty third NMOS transistor MN23, and the twenty fifth NMOS transistor MN25 form a current mirror structure.
  9. 9. The low temperature drift sectional compensation bandgap reference circuit of claim 5, wherein said twenty-sixth NMOS transistor MN26 and said twenty-seventh NMOS transistor MN27 in said bias circuit (4) are respectively the same size as said tenth NMOS transistor MN10 and said thirteenth NMOS transistor MN13, such that the current flowing through said twenty-sixth NMOS transistor MN26 is equal to the current flowing through said thirteenth NMOS transistor MN 13.
  10. 10. An integrated circuit, characterized in that a low temperature drift sectional compensation bandgap reference circuit according to any of claims 1 to 9 is integrated.

Description

Low-temperature drift sectional compensation band gap reference circuit Technical Field The invention relates to the technical field of analog integrated circuit design, in particular to a low-temperature drift sectional compensation band gap reference circuit. Background In the field of analog integrated circuits and digital-analog hybrid integrated circuits, a band gap reference circuit is an indispensable core basic module, and has the functions of providing voltage or current reference signals with stable precision and small influence by environmental factors for the whole electronic system, and the performance of the band gap reference circuit directly determines the working precision, the running stability and the long-term reliability of the subsequent all-stage circuits. The circuit is widely applied to core devices and modules such as low-dropout linear voltage regulators, analog-to-digital converters, digital-to-analog converters, sensor interface circuits, radio frequency transceivers, memories, various high-precision measuring instruments and the like, and covers a plurality of strategic key fields such as consumer electronics, industrial control, automotive electronics, medical equipment, aerospace and the like. The band gap reference circuit has various classical topological structures, and the core principle of the traditional band gap reference circuit is to utilize the negative temperature coefficient characteristic of the bipolar transistor and the positive temperature coefficient characteristic generated by the voltage difference between the base electrodes and the emitter electrodes of the two bipolar transistors to carry out weighted superposition, and realize stable reference voltage output insensitive to temperature through characteristic cancellation. In practical circuit design, the negative temperature coefficient characteristic of a bipolar transistor is difficult to reach an ideal first-order linearity level, and a temperature response curve has obvious high-order nonlinear curvature distortion. The non-ideal characteristic can lead the output voltage of the band-gap reference circuit to inevitably introduce second-order and higher-order temperature coefficients, and severely restrict the precision improvement of the band-gap reference. Therefore, in order to further improve the temperature stability of the reference circuit, it is necessary to design a targeted temperature coefficient compensation scheme, and to suppress the influence of the high-order temperature coefficient by introducing the segment compensation circuit, so as to realize the optimization and upgrading of the bandgap reference precision. Disclosure of Invention The invention aims to provide a low-temperature drift sectional compensation band gap reference circuit so as to solve the problems in the prior art. In order to achieve the above purpose, the invention adopts the following technical scheme: In a first aspect, the invention provides a low temperature drift sectional compensation band gap reference circuit, which comprises a starting circuit, a first-order compensation band gap reference circuit, a sectional compensation circuit and a bias circuit; The starting circuit is electrically connected with the first-order compensation band gap reference circuit, and is used for injecting current into the first-order compensation band gap reference circuit when power is supplied so as to separate from a degeneracy point; the first-order compensation band-gap reference circuit is electrically connected with the segment compensation circuit, and is used for providing band-gap reference voltage for eliminating a first-order temperature coefficient and providing a connection node for the segment compensation circuit; The segment compensation circuit is electrically connected with the bias circuit and is used for providing linear segment compensation current for the band gap reference voltage; The bias circuit is electrically connected with the first-order compensation band gap reference circuit and the segmentation compensation circuit respectively, and provides stable bias voltage for the first-order compensation band gap reference circuit and the segmentation compensation circuit. In some embodiments, the starting circuit includes a first PMOS transistor MP1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a first resistor R1; One end of the first resistor R1 is connected with a power supply voltage Vref, and the other end of the first resistor R1 is connected with the drain electrode of the first NMOS tube MN 1; The grid electrode of the first NMOS tube MN1 and the grid electrode of the second NMOS tube MN2 are connected with the drain electrode of the first NMOS tube MN1 in a sharing way; The grid electrode of the first PMOS tube MP1 is connected with a control signal VOEN, the sour