CN-121996027-A - Clock surge detection circuit

Abstract

The clock burst detection circuit comprises a clock generator, a counter and a detection unit. The clock generator receives an input clock signal and generates a reference clock signal having a higher frequency than the input clock signal when the input clock signal is at a first voltage. The counter counts a current accumulated number of periods passed by the reference clock signal when the input clock signal is at the first voltage. The detecting unit calculates a difference between a previous accumulation number and a current accumulation number after the input clock signal is changed from the first voltage to the second voltage. The detecting unit generates an alarm signal according to the difference between the current accumulation number and the previous accumulation number, and stores the current accumulation number as the previous accumulation number.

Inventors

• SHAO QIYI
• Wang Shengzong
• Wu Zhini

Assignees

• 熵码科技股份有限公司

Dates

Publication Date

20260508

Application Date

20251030

Priority Date

20241104

Claims (16)

1. 1. A clock spike detection circuit, comprising: A first clock generator configured to receive an input clock signal and generate a first reference clock signal when the input clock signal is at a first voltage, wherein a frequency of the first reference clock signal is higher than a frequency of the input clock signal; a first counter configured to count a first current accumulated number of cycles passed by the first reference clock signal when the input clock signal is in a count phase of the first voltage, and A first detecting unit configured to calculate a difference between a first previous accumulation number and the first current accumulation number after the input clock signal changes from the first voltage to the second voltage in a decision stage later than the counting stage, and store the first current accumulation number as the first previous accumulation number after calculating the difference between the first previous accumulation number and the first current accumulation number, and generate a first alarm signal according to the difference between the first previous accumulation number and the first current accumulation number.
2. 2. The clock spike detection circuit of claim 1 further comprising: a first timing control unit configured to generate a first timing control signal when the input clock signal changes from the first voltage to the second voltage, and generate a first control signal by delaying the first timing control signal in the determination stage; The first detecting unit is triggered according to the first control signal to calculate the difference between the first previous accumulation number and the first current accumulation number.
3. 3. The clock spike detection circuit of claim 2 wherein the first timing control unit is further configured to generate a second control signal by delaying the first control signal during the determining phase; The first detecting unit is triggered according to the second control signal to generate the first alarm signal and store the first current accumulation number as the first previous accumulation number.
4. 4. The clock spike detection circuit of claim 3 wherein the first timing control unit is further configured to generate a third control signal by delaying the second control signal during the determining phase; wherein the first counter is reset upon receiving the third control signal.
5. 5. The clock spike detection circuit of claim 4 wherein the first timing control unit comprises: An SR latch comprising a set terminal configured to receive an inverted input clock signal, a reset terminal configured to receive the third control signal, a data output terminal configured to output the first timing control signal after the input clock signal becomes the second voltage, and And a delay control unit configured to generate the first control signal, the second control signal and the third control signal according to the first timing control signal.
6. 6. The clock spike detection circuit of claim 3 wherein the first detection unit comprises: A register configured to store the first current accumulation number as the first previous accumulation number upon receiving the second control signal, and A subtractor configured to subtract the first previous accumulation number from the first current accumulation number or to subtract the first current accumulation number from the first previous accumulation number, thereby calculating the difference between the first previous accumulation number and the first current accumulation number upon receiving the first control signal.
7. 7. The clock spike detection circuit of claim 6 wherein a first delay between the first timing control signal and the first control signal is longer than a computation time of the subtractor.
8. 8. The clock spike detection circuit of claim 6 wherein the subtractor comprises: A carry-ahead subtractor configured to successively subtract the first current accumulated number and the first previous accumulated number to calculate the difference between the first previous accumulated number and the first current accumulated number, and A register configured to be triggered by the first control signal to store the difference between the first previous accumulation number and the first current accumulation number.
9. 9. The clock spike detection circuit of claim 6 wherein the first detection unit further comprises comparison logic configured to generate the first alarm signal in the determination phase when the second control signal is received and when the difference between the first previous accumulation number and the first current accumulation number is greater than a fixed value.
10. 10. The clock spike detection circuit of claim 9 wherein the comparison logic circuit comprises: logic circuitry configured to successively obtain a comparison result between the difference value calculated by the subtractor and the predetermined value, and A register configured to be triggered by the second control signal to store the comparison result between the difference calculated by the subtractor and the predetermined value.
11. 11. The clock spike detection circuit of claim 9 wherein a second delay between the first control signal and the second control signal is longer than a computation time of the comparison logic circuit.
12. 12. The clock spike detection circuit of claim 1 wherein the first detection unit generates the first alarm signal when the difference between the first previous accumulation number and the first current accumulation number is greater than a predetermined value during the determination phase.
13. 13. The clock spike detection circuit of claim 1 wherein the first clock generator is disabled when the input clock signal is at the second voltage.
14. 14. The clock spike detection circuit of claim 1 further comprising: a third inverter configured to generate an inverted input clock signal by inverting the input clock signal; a second clock generator configured to receive the inverted input clock signal and generate a second reference clock signal when the inverted input clock signal is at the first voltage, wherein a frequency of the second reference clock signal is higher than a frequency of the inverted input clock signal; a second counter configured to count a second current accumulation number of the number of periods of the second reference clock signal, and The second detecting unit is configured to calculate a difference between a second previous accumulation number and the second current accumulation number after the inverted input clock signal is changed from the first voltage to the second voltage, generate a second alarm signal according to the difference between the second previous accumulation number and the second current accumulation number after the difference between the second previous accumulation number and the second current accumulation number is calculated, and store the second current accumulation number as the second previous accumulation number.
15. 15. The clock spike detection circuit of claim 14 further comprising: a second timing control unit configured to generate a second timing control signal when the inverted input clock signal changes from the first voltage to the second voltage, and generate a fourth control signal by delaying the second timing control signal; the second detecting unit is triggered to calculate the difference between the second previous accumulation number and the second current accumulation number according to the fourth control signal.
16. 16. The clock spike detection circuit of claim 15 wherein the second timing control unit is further configured to generate a fifth control signal by delaying the fourth control signal and to generate a sixth control signal by delaying the fifth control signal; the second detecting unit is triggered according to the fifth control signal to generate the second alarm signal, the second current accumulated number is stored as the second previous accumulated number, and the second counter is reset when receiving the sixth control signal.

Description

Clock surge detection circuit Technical Field The present disclosure relates to a burst detection circuit, and more particularly, to a burst detection circuit capable of detecting a burst of a clock signal. Background Clock signals are important components in electronic circuits that can be used as timing references for synchronous operation of components within the system. The precise periodicity of the clock signal ensures that data can be processed in a coordinated manner, thereby facilitating seamless execution of complex computational tasks. Therefore, even if small deviations or distortions (i.e., spikes) are generated in the clock signal, the circuit performance may be adversely affected. For example, a surge may cause misalignment of system states, erroneous sampling of data, signal disturbances, and thus may cause the entire circuit to malfunction or fail. Therefore, it is important to detect bursts of the clock signal to avoid system faults or failures. Disclosure of Invention An embodiment of the present disclosure provides a clock spike detection circuit. The clock burst detection circuit comprises a clock generator, a counter, a detection unit and a time sequence control unit. The clock generator receives an input clock signal and generates a first reference clock signal when the input clock signal is at a first voltage. The frequency of the reference clock signal is higher than the frequency of the input clock signal. The counter counts a current accumulated number of cycles (cycles) passed by the reference clock signal when the input clock signal is at the first voltage. The detecting unit calculates a difference between a previous accumulation number and a current accumulation number after the input clock signal is changed from the first voltage to the second voltage, generates an alarm signal according to the difference between the previous accumulation number and the current accumulation number after the difference between the previous accumulation number and the current accumulation number is updated, and stores the current accumulation number as the previous accumulation number. Drawings A more complete appreciation of the present disclosure can be derived by referring to the detailed description and claims when considered in connection with the figures, wherein like reference numbers refer to similar elements throughout the figures. FIG. 1 shows a clock spike detection circuit according to one embodiment of the present disclosure; FIG. 2 is a signal timing diagram of the clock spike detection circuit of FIG. 1 according to one embodiment of the present disclosure; FIG. 3 shows the logic circuit according to an embodiment of the present disclosure; FIG. 4 shows a clock spike detection circuit according to one embodiment of the present disclosure; FIG. 5 illustrates a method for detecting clock bursts of the input clock signal according to an embodiment of the disclosure. Detailed Description FIG. 1 shows a clock spike detection circuit 100 according to one embodiment of the present disclosure. The clock spike detection circuit 100 includes a clock generator 110, a counter 120 and a detection unit 130. In the present embodiment, the clock glitch detection circuit 100 may be configured to detect a glitch (glitch) in the input clock signal SIG CKIN switched between the voltages V1 and V2. The clock generator 110 may receive the input clock signal SIG CKIN, generate the reference clock signal SIG REF1 when the input clock signal SIG CKIN is at the voltage V1, and stop generating the reference clock signal SIG REF1 when the input clock signal SIG CKIN is at the voltage V2. That is, the clock generator 110 may be enabled when the input clock signal SIG CKIN is at the voltage V1 and may be disabled when the input clock signal SIG CKIN is at the voltage V2. In the present embodiment, the voltage V1 may be higher than the voltage V2, however, the present disclosure is not limited thereto. In the present embodiment, the reference clock signal SIG REF1 may have a frequency higher than that of the input clock signal SIG CKIN. The counter 120 may count the current accumulated number of periods of the reference clock signal SIG REF1 when the input clock signal SIG CKIN is at the voltage V1 in order to measure the duration of the input clock signal SIG CKIN at the voltage V1. For example, the counter 120 may increment by 1 on each rising or falling edge of the reference clock signal SIG REF1. In such cases, the counter 120 may measure the length of the duration of the input clock signal SIG CKIN at voltage V1 as a function of the number of cycles that the reference clock signal SIG REF1 has passed over the duration. In the present embodiment, since the voltage V1 is higher than the voltage V2, the duration of the input clock signal SIG CKIN maintained at the voltage V1 may also be referred to as "on time" of the input clock signal SIG CKIN, and the duration of the input clock signal SIG CKIN maintained