CN-121996051-A - Branch prediction unit power consumption management method and device

CN121996051ACN 121996051 ACN121996051 ACN 121996051ACN-121996051-A

Abstract

The invention discloses a branch prediction unit power consumption management method and device, the method comprises the steps of setting a multi-stage branch predictor and a low power consumption control logic coupled with the multi-stage branch predictor in a processor core micro-architecture, wherein the multi-stage branch predictor comprises three-stage predictors which are sequentially accessed in a pipeline, each stage of predictors gradually increases from front to back in terms of hardware resource consumption and prediction accuracy, monitoring the prediction conditions of each stage of predictors in real time through the low power consumption control logic, closing all predictors behind a predictor which meets the prediction requirement for the first time in a first preset time according to the front to back sequence, and dividing branch jump addresses into a high-order address segment and a low-order address segment in predictors except the first-stage predictor by BTB (base to base) in different storage blocks, and setting a tag register for taking the high-order address as a tag index.

Inventors

LI DONGSHENG
ZHANG XIRAN
WU YE
LI WEI

Assignees

南京英麒智能科技有限公司

Dates

Publication Date: 20260508
Application Date: 20251226

Claims (9)

1. A power consumption management method for a branch prediction unit is characterized by comprising the steps of arranging a multi-stage branch predictor and low-power consumption control logic which is coupled with the multi-stage branch predictor in a processor core micro-architecture, wherein the multi-stage branch predictor comprises three-stage predictors which are sequentially accessed in a pipeline, each stage of predictors gradually increases from front to back in terms of hardware resource consumption and prediction accuracy, the prediction conditions of each stage of predictors are monitored in real time through the low-power consumption control logic, and all predictors behind a first predictor meeting prediction requirements in preset time are closed according to the sequence from front to back.
2. The method of claim 1, wherein the BTB in the multi-level predictor other than the first-level predictor divides branch jump addresses into high-order address segments and low-order address segments and stores the high-order address segments in different memory blocks, a tag register is provided for taking the high-order address as a tag index, and a tag value is stored in a corresponding low-order address memory block, and if the tag value read from the low-order address memory block matches with the high-order segment address of the current program counter in a subsequent prediction access, the low-order address memory block is spliced with the low-order address in the low-order address memory block to generate a complete jump address.
3. The method of claim 2, wherein the first level predictor of the multi-level branch predictor comprises only BTB, the second level predictor comprises BTB and a base TAGE, the third level predictor comprises BTB and a global TAGE, and the global TAGE comprises multi-level memory blocks.
4. The method of claim 2, wherein when the first predictor that meets the prediction requirement is the second level predictor, the high-order address memory block is turned off after a predetermined time, and otherwise all memory blocks are required to be kept fully on and the third level predictor is turned on.
5. The method of claim 3, wherein when the first predictor that satisfies the prediction requirement is a third-level predictor, the prediction requirement is still satisfied after a preset time, at least one of the memory blocks or the high-order address memory blocks that are not accessed in the global TAGE is closed, otherwise, the memory blocks or the high-order address memory blocks are kept fully open.
6. The method of claim 1, wherein when the first predictor that satisfies the prediction requirement is the first level predictor, the second level predictor is turned on while the high-order address storage block of the second level predictor is turned off after a preset time, after the preset time, the high-order address storage block of the second level predictor is turned on if the second level predictor satisfies the prediction requirement, and after the preset time, the high-order address storage block of the second level predictor is turned on, and if the second level predictor satisfies the prediction requirement, the high-order address storage block of the third level predictor is turned on.
7. The method of claim 1, wherein the prediction requirement comprises a direction of the jump and a target address of the jump is predicted correctly.
8. A branch prediction unit power consumption management device is characterized by comprising a multi-stage branch predictor and low-power consumption control logic, wherein the low-power consumption control logic is coupled with the multi-stage branch predictor, the multi-stage branch predictor at least comprises a multi-stage hardware resource overhead and a sub-stage predictor with prediction capacity increasing step by step from front to back, the low-power consumption control logic is configured to monitor the prediction accuracy of each sub-stage predictor in real time, and all the sub-stage predictors behind the first sub-stage predictor meeting the prediction requirement are closed according to the sequence from front to back.
9. The apparatus of claim 1, wherein the multi-stage branch predictor is divided into three stages, wherein the BTBs of the second and third stage predictors divide the branch jump address into a high order address field and a low order address field for separate storage, and are provided with a tag register for indexing the high order address as a tag.

Description

Branch prediction unit power consumption management method and device Technical Field The invention relates to a computer processor design, in particular to a branch prediction unit power consumption management method and a device. Background Modern high performance processors commonly employ multi-stage pipeline architectures to increase instruction throughput. The frequent occurrence of branch instructions makes the branch prediction unit a critical component in determining pipeline efficiency. In pursuit of high prediction accuracy, mainstream designs commonly configure a large-capacity branch target buffer (Branch Target Buffer, BTB) and a global history-based TAGE (TAgged GEometric) direction predictor, the memory array of which is typically composed of registers and Random Access Memory (RAM). The digital circuit principle shows that the dynamic power consumption is mainly caused by the charge and discharge of the load capacitor and the instantaneous short-circuit current of the MOS tube, and the read-write operation of the high-capacity RAM is one of the main contributors of the dynamic power consumption. In the edge computing and terminal application scenarios that pursue high performance and consider the power consumption endurance, the power consumption ratio of the branch prediction unit cannot be ignored. In the prior art, coarse granularity means such as dynamic voltage frequency adjustment (DVFS) or Power Gating (Power Gating) are mainly adopted at the SoC level, for example, power Policy Unit (PPU) architecture of an ARM, a control object of the SoC is an entire processor subsystem or a processor core, the adjustment granularity is only "full on" or "full off", and differentiated management cannot be performed on a single functional unit in the core and only products of the SoC are adapted. At present, low-power-consumption design inside a processor core depends on coding styles of Electronic Design Automation (EDA) tools and designers, and an active power consumption management strategy aiming at the working characteristics of a branch prediction unit is lacking, so that the input of prediction resources cannot be dynamically adjusted according to the running time behavior, and a later-stage high-capacity predictor is still in an inactive state under a light load scene, so that unnecessary power consumption waste is caused. Disclosure of Invention The invention aims to provide a branch prediction unit power consumption management method and device which can finely control power consumption units of predictors at all levels, greatly reduce energy consumption, and have strong universality without system level adaptation. The technical scheme is that the branch prediction unit power consumption management method comprises the steps of setting a multi-stage branch predictor and low-power consumption control logic coupled with the multi-stage branch predictor in a processor core micro-architecture, wherein the multi-stage branch predictor comprises three-stage predictors which are sequentially accessed in a pipeline, each stage of predictors gradually increases from front to back in terms of hardware resource consumption and prediction accuracy, monitoring the prediction conditions of each stage of predictors in real time through the low-power consumption control logic, and closing all predictors behind the first predictor meeting the prediction requirement in preset time according to the sequence from front to back. By directly integrating the multi-level predictor with the low-power control logic in the processor core micro-architecture, a power management unit at the SoC level is not needed, and the design and adaptation cost at the system level is greatly reduced. The low power control logic monitors the prediction condition of each stage of branch predictors in real time and dynamically adjusts the opening and closing states of the predictors according to the prediction condition, so that a processor core can adaptively determine the depth of a prediction resource to be used according to the real-time characteristic of program operation, when the program branch behavior is simple and the front stage predictors are enough to cope, the predictors with larger power consumption at the rear side can be shut down on occasion, the dynamic power consumption is directly eliminated from the source, so that the fine self-adaptive power consumption management matched with the program load is realized on the source, the problem of coarse control granularity in the prior art is solved, and the method is applicable to all hierarchical predictors in the prior art, does not need system level cooperation and has strong universality. Preferably, the branch jump addresses are divided into a high-order address segment and a low-order address segment by BTB in the predictors except the first-order predictors, which are stored in different storage blocks, a tag register for taking the high-order address as a tag i