CN-121996052-A - SATA controller low-power consumption management device and method

CN121996052ACN 121996052 ACN121996052 ACN 121996052ACN-121996052-A

Abstract

The invention discloses a SATA controller low-power consumption management device and a method, which relate to the technical field of SATA solid state disks and are integrated on an SoC chip. The integrated SATA physical layer and SATA control unit acts as an independent power domain, and when DEVSLP signals are active, power is turned off, and simultaneously, the power consumption sources are cut off by matching with closing clock units such as a phase-locked loop and a crystal oscillator clock, a CPU and the like, so that the SoC chip enters the lowest power consumption state. And the entry and exit flow of DEVSLP low-power consumption modes is realized through the cooperation of software and hardware, so that data loss and command abnormality are avoided.

Inventors

LIU HAILIANG
Mou Xuewen
ZHANG ZUYANG
LI CHAO
HUANG RUI
MA YI
XIONG WEI

Assignees

芯盛智能科技(湖南)有限公司

Dates

Publication Date: 20260508
Application Date: 20260408

Claims (6)

1. The SATA controller low power consumption management device is characterized by being integrated on an SoC chip and comprising a SATA physical layer unit, a SATA control unit, a crystal oscillator clock unit, a clock gating unit, a phase-locked loop unit, a power consumption management unit and a configuration register unit, wherein: The SATA physical layer unit is used for realizing a SATA physical layer protocol function; The SATA control unit is connected with the SATA physical layer unit, and realizes physical integration by sharing an independent power domain E1, and is used for realizing functions of a link layer, a transmission layer and a command layer above a SATA protocol physical layer; the crystal oscillator clock unit is used for receiving the ref_clk clock signal input to the SoC chip and inputting the ref_clk clock signal to the phase-locked loop unit and the clock gating unit; The clock gating unit is used for starting and closing a ref_clk clock signal input to the SATA physical layer unit, and a control signal of the clock gating unit is from a configuration register of the configuration register unit; The phase-locked loop unit is used for doubling the ref_clk clock input by the crystal oscillator clock unit to different frequencies required by each unit of the SoC; The power consumption management unit is used for receiving a deep sleep signal DEVSLP sent by a host end and performing jitter elimination processing, and controlling the on and off of each power domain of the SoC chip, the on and off of the phase-locked loop unit and the crystal oscillator clock unit and the off of an input clock of the SATA physical layer unit when the power domains enter and exit a low power consumption mode; The configuration register unit is used for receiving the configuration values of the CPU to each register and transmitting the configuration values to the clock gating unit, the crystal oscillator clock unit, the power consumption management unit, the SATA physical layer unit and the SATA control unit, and simultaneously receiving the state information of the units and storing the state information to the corresponding registers.
2. The SATA controller low power consumption management apparatus of claim 1 wherein said SATA physical layer unit is coupled to a host SATA interface through a SATA_IF interface.
3. The SATA controller low power consumption management apparatus of claim 1, wherein said ref_clk clock signal is input to said SATA physical layer unit as a reference clock required for operation of said SATA physical layer unit, said reference clock being turned on and off by said clock gating unit in response to low power consumption control requirements.
4. The SATA controller low power consumption management apparatus of claim 1 wherein said SoC chip further comprises a CPU, a DDR and an on-chip cache, said SATA control unit further being configured to interact with said CPU, DDR and on-chip cache at a command layer to respectively implement functions of analyzing SATA commands, transmitting DMA commands, and reading/writing IO data.
5. A SATA controller low power consumption management method is characterized in that the method is applied to the SATA controller low power consumption management device as claimed in any one of claims 1 to 4, and comprises the following steps: The host pulls up the deep sleep signal DEVSLP, enabling the device side to enter DEVSLP a low power state; The CPU receives DEVSLP pull-up interrupt, stops receiving SATA commands, discards non-executed SATA commands, processes and waits for the execution of the executing SATA commands to finish; The CPU performs preparation work before power failure, including data downloading to a flash memory, table entry updating, register backup and firmware variable backup; After the preparation work before power failure is completed, the CPU configures a devslp _start register of the power consumption management unit to be high level, starts the power consumption management unit to start DEVSLP a low-power consumption flow, and enters a state of waiting for interruption; The power consumption management unit judges whether the current DEVSLP signal is in a high level or not, if so, the state that DEVSLP is not needed to be entered currently is indicated, the execution of the low-power consumption flow is finished, and the CPU receives DEVSLP to interrupt the execution and exit the low-power consumption flow; If the current DEVSLP signal is at high level, the low-power consumption flow is started, the power consumption management unit outputs a control signal to close clocks of the CPU and the SATA physical layer unit, resets, opens isolation control signals of all power domains to isolate all power domains, closes power of all power domains of the SoC chip, closes the phase-locked loop unit and the crystal oscillator clock unit, and the equipment end enters DEVSLP low-power consumption state.
6. The SATA controller low power consumption management method of claim 5 further comprising: When the host end needs the equipment end to exit the low power consumption mode, the deep sleep signal DEVSLP is pulled down, the power consumption management component immediately exits the DEVSLP low power consumption state after detecting the change of the deep sleep signal DEVSLP, and sequentially starts the crystal oscillator clock unit and the phase-locked loop unit to resume clock supply, then the power consumption management component starts the power supply of each power domain, closes the Isolation control signal of each power domain, resumes the normal connection of each power domain, starts the clocks of the CPU and the SATA physical layer unit, resets the related modules to resume normal operation of each module, the CPU wakes up from the waiting interruption state, reads the register data and the firmware variables backed up before, resumes the normal operation state of the system, resumes receiving and executing SATA commands at the same time, and the equipment end resumes the normal operation mode.

Description

SATA controller low-power consumption management device and method Technical Field The invention relates to the technical field of SATA solid state disks, in particular to a device and a method for managing low power consumption of a SATA controller. Background With the rapid development of mobile terminals such as notebook computers, tablet computers and portable devices, and the wide deployment of large-scale data center storage servers, the application upgrading of scenes such as industrial control, vehicle-mounted systems and internet of things devices, and the like, increasingly strict requirements are put on the power consumption of the storage devices. For a storage server of a data center, the total power consumption is extremely high, the power consumption of each SATA device, especially the standby power consumption, can be reduced remarkably, the electricity charge expenditure and the heat dissipation cost can be reduced, the development trend of green calculation is met, in addition, the SATA device is extremely sensitive to the power consumption and the stability of the storage device in the scenes of industrial control, vehicle-mounted systems, internet of things devices and the like, and the low-power consumption SATA design is beneficial to reducing the heat dissipation of the system and improving the running stability and the service life of the devices. The SATA 3.2 protocol introduces a device sleep (DEVSLP) function, DEVSLP is a sideband signal, is efficient, and needs to be supported by a host side and a device side simultaneously to use the low-power consumption function. When the signal is in high level, the equipment end enters an extremely low power consumption mode, so that standby power consumption is further reduced, and a near zero power consumption state is supported. The low power design requirements of SATA are a result of mobility, data center energy efficiency, protocol evolution, SSD technology and market demand co-driven. The method and the system remarkably reduce the whole energy consumption of the system and adapt to the full-scene requirement from the portable equipment to the data center through the cooperative optimization of hardware and a protocol while meeting the storage performance. Along with the popularization of PCIe/NVMe interfaces, the design concept of SATA with low power consumption is inherited and developed, and the energy efficiency evolution of the storage technology is further promoted. Disclosure of Invention The invention aims to overcome the defects of the prior art, and provides a SATA controller low-power consumption management device and a method thereof, which enable an SoC chip to enter a lowest power consumption state, improve the flexibility of entering and exiting a low-power consumption mode and meet the low-power consumption requirements of multiple scenes. The aim of the invention is realized by the following technical scheme: In a first aspect, a low power consumption management device of a SATA controller is integrated on an SoC chip, and includes a SATA physical layer unit, a SATA control unit, a crystal oscillator clock unit, a clock gating unit, a phase locked loop unit, a power consumption management unit, and a configuration register unit, where: The SATA physical layer unit is used for realizing a SATA physical layer protocol function; The SATA control unit is connected with the SATA physical layer unit, and realizes physical integration by sharing an independent power domain E1, and is used for realizing functions of a link layer, a transmission layer and a command layer above a SATA protocol physical layer; the crystal oscillator clock unit is used for receiving the ref_clk clock signal input to the SoC chip and inputting the ref_clk clock signal to the phase-locked loop unit and the clock gating unit; The clock gating unit is used for starting and closing a ref_clk clock signal input to the SATA physical layer unit, and a control signal of the clock gating unit is from a configuration register of the configuration register unit; The phase-locked loop unit is used for doubling the ref_clk clock input by the crystal oscillator clock unit to different frequencies required by each unit of the SoC; The power consumption management unit is used for receiving a deep sleep signal DEVSLP sent by a host end and performing jitter elimination processing, and controlling the on and off of each power domain of the SoC chip, the on and off of the phase-locked loop unit and the crystal oscillator clock unit and the off of an input clock of the SATA physical layer unit when the power domains enter and exit a low power consumption mode; The configuration register unit is used for receiving the configuration values of the CPU to each register and transmitting the configuration values to the clock gating unit, the crystal oscillator clock unit, the power consumption management unit, the SATA physical layer unit and the SATA control unit, and si