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CN-121996055-A - Power consumption regulating and reducing device and power consumption regulating and reducing method

CN121996055ACN 121996055 ACN121996055 ACN 121996055ACN-121996055-A

Abstract

The invention provides a power consumption reducing device and a power consumption reducing method. The power manager includes a model acceleration algorithm. The first master controller is used for outputting a first active transmission signal. The model acceleration algorithm is used for controlling a clock source of the processor or a power supply of the processor according to the first active transmission signal so as to reduce the power consumption of the processor.

Inventors

  • WANG ZHENGJIE

Assignees

  • 新唐科技股份有限公司

Dates

Publication Date
20260508
Application Date
20250528
Priority Date
20241107

Claims (10)

  1. 1. A power consumption reduction apparatus, comprising: a first master controller for outputting a first active transmission signal; A processor, and A power manager, comprising: a model acceleration algorithm is used for controlling a clock source of the processor or a power supply of the processor according to the first active transmission signal so as to reduce power consumption of the processor.
  2. 2. The power consumption reduction apparatus according to claim 1, comprising: The first active transmission signal comprises one of a peripheral direct memory access signal and a direct memory access signal; wherein the first master comprises one of a direct memory access controller and a peripheral direct memory access controller; the power consumption reducing device comprises a microcontroller, and the processor is positioned in the microcontroller.
  3. 3. The power consumption reduction apparatus according to claim 1, comprising: The power manager further comprises an event fusion engine, wherein the event fusion engine is used for receiving and outputting an integrated signal according to a plurality of signals; Wherein the plurality of signals includes the first actively-transmitted signal.
  4. 4. The power consumption reduction apparatus according to claim 3, comprising: The power manager further comprises a neural network inference engine, which outputs a first relay signal or a second relay signal according to the integrated signal and the model acceleration algorithm.
  5. 5. The power consumption reduction apparatus according to claim 4, comprising: The power manager further includes a clock control logic that adjusts a clock frequency of the processor according to the first relay signal.
  6. 6. The power consumption reduction apparatus according to claim 4, comprising: the power manager further includes a power control logic that adjusts a voltage of the processor according to the second relay signal.
  7. 7. The power consumption reduction apparatus according to claim 1, comprising: The power consumption reducing device is used for a first platform and a second platform; The model acceleration algorithm reduces the power consumption of the processor according to a first event of the first platform.
  8. 8. The power consumption reduction apparatus according to claim 7, comprising: The model acceleration algorithm reduces the power consumption of the processor according to a second event of the second platform; Wherein the first platform and the second platform are different from each other.
  9. 9. A method for reducing power consumption, comprising: Outputting a first active transmission signal by a first master controller; Outputting a second active transmission signal by a second master controller; controlling a clock source of a processor or a power source of the processor according to the first active transmission signal by means of a model acceleration algorithm of a power manager to reduce a power consumption of the processor, and Controlling the clock source of the processor or the power supply of the processor according to a second active transmission signal by means of the model acceleration algorithm of the power supply manager so as to reduce the power consumption of the processor; wherein none of the first active transmission signal and the second active transmission signal is directly input to the processor; Wherein the first master and the second master each comprise one of a direct memory access controller and a peripheral direct memory access controller.
  10. 10. The method for reducing power consumption of claim 9, comprising: The power consumption reducing method is executed by a microcontroller, and the processor, the first master controller and the second master controller are positioned in the microcontroller.

Description

Power consumption regulating and reducing device and power consumption regulating and reducing method Technical Field The present invention relates to a power saving device and a power saving method, and more particularly to a power saving device and a power saving method. Background Currently, in general, low power designs of Micro controllers (Micro ControlUnit, MCU) and/or microprocessors (Micro Processing Unit, MPU), software developers need to have a certain knowledge about the voltage and power control of a target platform. Therefore, the software developer needs much time to research and read the specification in developing the program, and the control program code is complex, and unexpected errors are easy to generate, so that the development cost and the development time are increased. Disclosure of Invention This summary is intended to provide a simplified summary of the disclosure so that the reader will have a basic understanding of the disclosure. This summary is not an extensive overview of the disclosure and is intended to neither identify key/critical elements of the embodiments of the invention nor delineate the scope of the invention. One aspect of the present disclosure relates to a power consumption reduction device. The power consumption regulating device comprises a first main controller, a processor and a power supply manager. The power manager includes a model acceleration algorithm. The first master controller is used for outputting a first active transmission signal. The model acceleration algorithm is used for controlling a clock source of the processor or a power supply of the processor according to the first active transmission signal so as to reduce the power consumption of the processor. In one embodiment, the first active transfer signal comprises one of a peripheral direct memory access signal and a direct memory access signal, wherein the first master comprises one of a direct memory access controller and a peripheral direct memory access controller, wherein the power consumption reduction device comprises a microcontroller, and the processor is located in the microcontroller. In one embodiment, the power manager further includes an event fusion engine configured to receive and output an integrated signal according to a plurality of signals, wherein the plurality of signals includes the first active transmission signal. In one embodiment, the power manager further includes a neural network inference engine that outputs a first control signal relay signal or a second control signal relay signal according to the integrated signal and the model acceleration algorithm. In an embodiment, the power manager further includes a clock control logic, and the clock control logic adjusts a clock frequency of the processor according to the first relay signal control. In an embodiment, the power manager further includes a power control logic, and the power control logic adjusts a voltage level of the processor according to the second relay signal control. In one embodiment, the power consumption reducing device is used for a first platform and a second platform, wherein the model acceleration algorithm reduces the power consumption of the processor according to a first event of the first platform. In one embodiment, the model acceleration algorithm reduces the power consumption of the processor according to a second event of the second platform, wherein the first platform and the second platform are different from each other. Another aspect of the disclosure relates to a method for reducing power consumption, comprising outputting a first active transmission signal by a first master controller, outputting a second active transmission signal by a second master controller, controlling a clock source of a processor or a power source of the processor according to the first active transmission signal by a model acceleration algorithm of a power manager to reduce power consumption of the processor, and controlling the clock source of the processor or the power source of the processor according to the second active transmission signal by the model acceleration algorithm of the power manager, wherein neither the first active transmission signal nor the second active transmission signal is directly input to the processor, and wherein each of the first master controller and the second master controller includes one of a direct memory access controller and a peripheral direct memory access controller. In one embodiment, a microcontroller performs the power down method and the processor is located within the microcontroller. Therefore, according to the technical content of the present invention, the power consumption adjustment device and the power consumption adjustment method according to the embodiments of the present invention enable the processor to adjust the power consumption in real time through the neural model algorithm, so as to achieve the effect of low power consumption (low power) adjus