CN-121996143-A - Flash memory controller and data reading method thereof

Abstract

The invention relates to a flash memory controller and a data reading method thereof. The flash memory controller includes a controller circuit and a scheduling circuit. The controller circuit receives a multi-plane read command signal sent by the host device, so as to respectively read data of a plurality of storage pages corresponding to the address information on a plurality of memory planes in the flash memory according to the recorded address information, store the plurality of first read commands in a first waiting list, and store a plurality of second read commands in a second waiting list. The scheduling circuit is used for reordering the read commands temporarily stored in the first waiting list and the second waiting list so as to stagger a plurality of first data output time periods and a plurality of second data output time periods.

Inventors

• LI FAHAO

Assignees

• 慧荣科技股份有限公司

Dates

Publication Date

20260508

Application Date

20241104

Claims (20)

1. 1. A flash memory controller for coupling to at least one flash memory via a specific bus, the at least one flash memory comprising a plurality of memory planes, each memory plane comprising a plurality of memory blocks, each block comprising a plurality of memory pages, and the flash memory controller comprising: a controller circuit for receiving a multi-plane read command signal sent by a host device to read a plurality of data corresponding to a plurality of storage pages of the address information on the plurality of memory planes in the at least one flash memory according to an address information recorded in the multi-plane read command signal, the controller circuit having a plurality of wait lists (PENDING LIST) corresponding to the plurality of memory planes, respectively, and A scheduling circuit (scheduler) coupled to the controller circuit for reordering the data stored in the plurality of waiting lists; The controller circuit converts the multi-plane read command signals into read command signals corresponding to the memory planes, wherein the read command signals include a plurality of first read commands for reading a plurality of sub-pages of a memory page on a first memory plane and a plurality of second read commands for reading a plurality of sub-pages of a memory page on a second memory plane, the controller circuit is used for suspending the first read commands in a first waiting list, suspending the second read commands in a second waiting list, and the scheduling circuit is used for reordering the first read commands buffered in the first waiting list and reordering the second read commands buffered in the second waiting list, so that a plurality of first data output periods respectively corresponding to the first read commands in the first waiting list are staggered without overlapping the second data output periods respectively corresponding to the second read commands in the first waiting list.
2. 2. The flash memory controller of claim 1, wherein the plurality of first read commands correspond to read times (tR) of different time periods, and the plurality of first data output periods and the plurality of second data output periods are data output periods from the at least one flash memory to the flash memory controller over the particular bus.
3. 3. The flash memory controller of claim 1, wherein the controller circuit comprises: a front-end circuit for receiving the multi-plane read command signal sent by the host device; A conversion layer (flash translation layer, FTL) circuit coupled to the front-end circuit for converting the multi-plane read command signal into a plurality of read command signals corresponding to the plurality of memory planes, and The back-end circuit is coupled to the translation layer circuit for suspending the plurality of first read commands in the first waiting list, suspending the plurality of second read commands in the second waiting list, and sequentially reading the first memory plane and the second memory plane according to the reordered information in the first waiting list and the second waiting list ( sequen tial rea d).
4. 4. The flash memory controller of claim 1 wherein the scheduling circuit is configured to reorder the plurality of first read commands registered in the first wait list and reorder the plurality of second read commands registered in the second wait list to minimize a latency of the particular bus.
5. 5. The flash memory controller of claim 1 wherein the first read commands are used to read data of a plurality of sub-pages of one of the memory pages corresponding to the specific address on the first memory plane and the second read commands are used to read data of a plurality of sub-pages of another of the memory pages corresponding to the specific address on the second memory plane.
6. 6. The flash memory controller of claim 1 wherein the scheduling circuit is configured to calculate a plurality of expected start time points and a plurality of expected end time points for the plurality of first data output time periods and a plurality of expected start time points and a plurality of expected end time points for the plurality of second data output time periods in order to minimize a latency of the particular bus to reorder the information buffered in the first and second wait lists.
7. 7. The flash memory controller of claim 1 wherein when the controller circuit determines to issue a specific read command corresponding to an idle memory plane, the scheduling circuit determines a sub-page type of a page to be read by the specific read command such that a specific data output period corresponding to the specific read command is staggered from the first data output periods and the second data output periods.
8. 8. The flash memory controller of claim 7 wherein the sub-page type is a j-th sub-page, a read time corresponding to the j-th sub-page is T R (j), a start time point of a read task on an i-th memory plane is T left (i)＝T start (i)-T cur , An end time point of the read task is T right (i)＝T end (i)-T cur , wherein T cur is a current time point, T start (i) is an expected start time point of the read task, T end (i)＝T start (i)+t Dout ,t Dout is a length of a corresponding data output time period, and the scheduling circuit is configured to determine the sub-page type such that T R (j) satisfies at least one of the following two inequality conditions: t R (j)+t Dout ＜T left (i), or t R (j)>T right (i)。
9. 9. The flash memory controller of claim 1 wherein when the controller circuit determines to issue a particular read command corresponding to an empty memory plane, the scheduling circuit determines a type of sub-page that the particular read command is to read to minimize a latency of the particular bus.
10. 10. The flash memory controller of claim 9 wherein the sub-page type is a j-th sub-page, a read time corresponding to the j-th sub-page is T R (j), a start time point of a read task on an i-th memory plane is T left (i)＝T start (i)-T cur , An ending time point of the read task is T right (i)＝T end (i)-T cur , wherein T cur is a current time point, T start (i) is an expected starting time point of the read task, T end (i)＝T start (i)+t Dout ,t Dout is a length of a corresponding data output time period, and the scheduling circuit is configured to determine the sub-page type according to the following conditions: Min(Min(|t R (j)+t Dout -T left (i)|),Min(|t R (j)-T right (i)|))。
11. 11. A data reading method of a flash memory controller for coupling to at least one flash memory via a specific bus, the at least one flash memory including a plurality of memory planes, each memory plane including a plurality of memory blocks, each block including a plurality of memory pages, the data reading method comprising: Receiving a multi-plane read command signal sent by a host device by using a controller circuit, wherein the controller circuit is provided with a plurality of waiting lists corresponding to a plurality of memory planes respectively, and the plurality of memory pages corresponding to the address information on the plurality of memory planes in the at least one flash memory are respectively read according to the address information recorded by the multi-plane read command signal; converting the multi-plane read command signal into a plurality of read command signals corresponding to the plurality of memory planes, the plurality of read command signals including a plurality of first read commands for reading a plurality of sub-pages of a memory page on a first memory plane and a plurality of second read commands for reading a plurality of sub-pages of a memory page on a second memory plane; temporarily storing the first read commands in a first waiting list, temporarily storing the second read commands in a second waiting list, and Reordering the first read commands registered in the first waiting list and reordering the second read commands registered in the second waiting list, so that the first data output periods corresponding to the first read commands in the first waiting list are staggered and do not overlap the second data output periods corresponding to the second read commands in the second waiting list.
12. 12. The method of claim 11, wherein the plurality of first read commands correspond to read times (tR) of a plurality of different time periods, and the plurality of first data output periods and the plurality of second data output periods are data output periods from the at least one flash memory to the flash memory controller via the specific bus.
13. 13. The data reading method of claim 11, further comprising: using a front-end circuit to receive the multi-plane read command signal sent by the host device; converting the multi-plane read command signal into a plurality of read command signals corresponding to the plurality of memory planes, and The method comprises the steps of suspending the plurality of first read commands in the first waiting list, suspending the plurality of second read commands in the second waiting list, and respectively performing a sequential read on the first memory plane and the second memory plane according to the reordered information in the first waiting list and the second waiting list.
14. 14. The data reading method of claim 11, further comprising: Reordering the first read commands registered in the first waiting list and reordering the second read commands registered in the second waiting list to minimize a waiting time of the specific bus.
15. 15. The method of claim 11, wherein the first read commands are used for reading data of a plurality of sub-pages of one page corresponding to the specific address on the first memory plane, and the second read commands are used for reading data of a plurality of sub-pages of another page corresponding to the specific address on the second memory plane.
16. 16. The data reading method of claim 11, further comprising: In the reordering, a plurality of expected start time points and a plurality of expected end time points of the plurality of first data output time periods and a plurality of expected start time points and a plurality of expected end time points of the plurality of second data output time periods are calculated to minimize a latency of the specific bus to reorder the information buffered in the first waiting list and the second waiting list.
17. 17. The data reading method of claim 11, further comprising: When a specific read command corresponding to an idle memory plane is determined to be issued, determining a sub-page type of a page to be read by the specific read command, and staggering a specific data output period corresponding to the specific read command from the first data output periods and the second data output periods.
18. 18. The method of claim 17, wherein the sub-page type is a j-th sub-page, a read time corresponding to the j-th sub-page is T R (j), a start time point of a read task on an i-th memory plane is T left (i)＝T start (i)-T cur , An end time point of the read task is T right (i)＝T end (i)-T cur , wherein T cur is a current time point, T start (i) is an expected start time point of the read task, and T end (i)＝T start (i)+t Dout ,t Dout is a length of a corresponding data output time period, and the data read method further comprises: Determining the sub-page type such that t R (j) satisfies at least one of the following two inequality conditions: t R (j)+t Dout ＜T left (i), or t R (j)>T right (i)。
19. 19. The data reading method of claim 11, further comprising: when it is determined to issue a specific read command corresponding to a free memory plane, a type of a sub-page that the specific read command uses to read is determined to minimize a latency of the specific bus.
20. 20. The method of claim 19, wherein the sub-page type is a j-th sub-page, a read time corresponding to the j-th sub-page is T R (j), a start time point of a read task on an i-th memory plane is T left (i)＝T start (i)-T cur , An end time point of the read task is T right (i)＝T end (i)-T cur , wherein T cur is a current time point, T start (i) is an expected start time point of the read task, and T end (i)＝T start (i)+t Dout ,t Dout is a length of a corresponding data output time period, and the data read method further comprises: determining the sub-page type according to the following conditions: Min(Min(|t R (j)+t Dout -T left (i)|),Min(|t R (j)-T right (i)|))。

Description

Flash memory controller and data reading method thereof Technical Field The present invention relates to a flash memory reading mechanism, and more particularly, to a flash memory controller and a data reading method of the flash memory controller. Background Generally, in a sequential read operation or scenario in which a conventional flash memory device operates, a conventional flash memory controller issues a multi-plane read command to a flash memory to read a plurality of data of a plurality of memory pages having a same memory page type at a same address of a plurality of different memory planes, and the plurality of data of the plurality of memory pages are first read out and buffered in a buffer within the flash memory, and then transferred from the buffer to the conventional flash memory controller through a bus. However, since the read times of the plurality of memory pages having the same memory page type are the same or similar, one data on one memory plane must wait until the other data on the other memory plane is transferred by the bus, which wastes a considerable amount of time in waiting for the bus to cause a drop in the read performance. Disclosure of Invention Therefore, an objective of the present invention is to provide a flash memory controller and a data reading method thereof, so as to solve the problems of the prior art. According to an embodiment of the invention, a flash memory controller is disclosed. The flash memory controller is used for being coupled to at least one flash memory through a specific bus, the at least one flash memory comprises a plurality of memory planes, each memory plane comprises a plurality of storage blocks, each block comprises a plurality of storage pages, and the flash memory controller comprises a controller circuit and a scheduling circuit. The controller circuit is used for receiving a multi-plane read command signal sent by a host device so as to respectively read a plurality of data of a plurality of storage pages corresponding to the address information on a plurality of memory planes in the at least one flash memory according to the address information recorded by the multi-plane read command signal, and the controller circuit is provided with a plurality of waiting lists (PENDING LIST) corresponding to the plurality of memory planes respectively. The scheduling circuit is coupled to the controller circuit and is used for reordering the data stored in the waiting lists. The controller circuit converts the multi-plane read command signal into read command signals corresponding to the plurality of memory planes, the read command signals including first read commands for reading sub-pages of a memory page on a first memory plane and second read commands for reading sub-pages of a memory page on a second memory plane. The controller circuit is used for temporarily storing the first read commands in a first waiting list and temporarily storing the second read commands in a second waiting list, and the scheduling circuit is used for reordering the first read commands temporarily stored in the first waiting list and reordering the second read commands temporarily stored in the second waiting list, so that a plurality of first data output time periods corresponding to the first read commands in the first waiting list are staggered and do not overlap with a plurality of second data output time periods corresponding to the second read commands in the second waiting list. According to another embodiment of the present invention, a data reading method of a flash memory controller is disclosed. The flash memory controller is configured to couple to at least one flash memory via a specific bus, the at least one flash memory including a plurality of memory planes, each memory plane including a plurality of memory blocks, each block including a plurality of memory pages. The data reading method comprises the steps of using a controller circuit to receive a multi-plane reading command signal sent by a host device, respectively reading a plurality of data of a plurality of storage pages corresponding to address information on a plurality of memory planes in at least one flash memory according to the address information recorded by the multi-plane reading command signal, converting the multi-plane reading command signal into a plurality of reading command signals corresponding to the plurality of memory planes, wherein the plurality of reading command signals comprise a plurality of first reading commands for reading a plurality of sub-storage pages of a storage page on a first memory plane and a plurality of second reading commands for reading a plurality of sub-storage pages of a storage page on a second memory plane, temporarily storing the plurality of first reading commands in a first waiting list, temporarily storing the plurality of second reading commands in a second waiting list, and respectively staggering the plurality of first reading commands tempora