CN-121996151-A - Memory device and method of operating the same

Abstract

A memory device and a method of operating the memory device are provided. The memory device includes a memory device and a memory controller for controlling the memory device by communicating with the memory device via a channel. The memory device includes a plurality of memory chips sharing a channel, and each of the plurality of memory chips includes a transfer driver and an adaptive body bias generator. A target memory chip selected by a memory controller among a plurality of memory chips includes a first adaptive body bias generator and a first transfer driver. The first adaptive body bias generator applies a first body bias to the first transfer driver in a write mode in which the target memory chip receives write data from the memory controller, and applies a second body bias in a read mode in which the target memory chip sends read data to the memory controller.

Inventors

• Sun Yingxun
• LIU ZHENGAO
• JIANG JINGTAI
• Jin Xiangrun
• Bian Chentao
• Cui Rongtun

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20250925

Priority Date

20241106

Claims (20)

1. 1. A storage device, comprising: Memory device, and A memory controller configured to control the memory device through the channel, Wherein the memory device includes a plurality of memory chips sharing the channel, the memory device being configured to select a target memory chip among the plurality of memory chips, Wherein the target memory chip comprises a first adaptive body bias generator and a first transfer driver, Wherein the first adaptive body bias generator is configured to apply a first body bias to the first transmission driver based on an operation mode including a write mode or a read mode, and Wherein the target memory chip is configured to receive write data from the memory controller in the write mode and to transmit read data to the memory controller in the read mode.
2. 2. The storage device of claim 1, wherein the first adaptive body bias generator is configured to: Applying a reverse body bias to the first transfer driver in a write mode, and A normal body bias is applied to the first transfer driver in a read mode.
3. 3. The memory device of claim 1, wherein the first transfer driver comprises a first n-type metal oxide semiconductor transistor and a first p-type metal oxide semiconductor transistor, Wherein the first n-type metal oxide semiconductor transistor and the first p-type metal oxide semiconductor transistor are connected to a data transmission line, the data transmission line is included in the channel, and Wherein the data transmission line is configured to transmit read data and receive write data.
4. 4. The memory device of claim 3, wherein the first adaptive body bias generator is configured to apply a reverse body bias to the first transfer driver in the write mode by: Applying a first bias voltage less than a ground voltage to a body of the first n-type metal oxide semiconductor transistor, and A second bias voltage greater than the supply voltage is applied to the body of the first p-type metal oxide semiconductor transistor.
5. 5. The memory device of claim 3, wherein the first adaptive body bias generator is configured to apply a normal body bias to the first transfer driver in the read mode by: applying a first bias voltage corresponding to a ground voltage to a body of the first n-type metal oxide semiconductor transistor, and A second bias voltage corresponding to a supply voltage is applied to the body of the first p-type metal oxide semiconductor transistor.
6. 6. A storage device according to claim 3, Wherein each of the one or more non-target memory chips of the plurality of memory chips not selected by the memory controller includes an on-die termination circuit connected to the data transmission line, Wherein each of the one or more non-target memory chips includes a corresponding adaptive body bias generator and a corresponding transfer driver, and Wherein the corresponding adaptive body bias generator is configured to apply the second body bias to the corresponding transmit driver based on the corresponding on-die termination circuit being enabled.
7. 7. The storage device of claim 6, Wherein the one or more non-target memory chips comprise a first non-target memory chip comprising enabled first on-die termination circuitry and a second non-target memory chip comprising disabled second on-die termination circuitry, Wherein the first non-target memory chip includes a second adaptive body bias generator and a second transfer driver, an Wherein the second non-target memory chip includes a third adaptive body bias generator and a third transfer driver.
8. 8. The memory device of claim 7, wherein the second adaptive body bias generator is configured to apply a normal body bias to the second transmission driver, and Wherein the third adaptive body bias generator is configured to apply a reverse body bias to the third transmission driver.
9. 9. The memory device of claim 8, wherein the third transfer driver comprises a second n-type metal oxide semiconductor transistor and a second p-type metal oxide semiconductor transistor, Wherein the second n-type metal oxide semiconductor transistor and the second p-type metal oxide semiconductor transistor are connected to the data transmission line, an Wherein the third adaptive body bias generator is configured to apply a reverse body bias to the third transmission driver by: Applying a first bias voltage less than a ground voltage to a body of a second n-type metal oxide semiconductor transistor, and A second bias voltage greater than the supply voltage is applied to the body of the second p-type metal oxide semiconductor transistor.
10. 10. The memory device of claim 8 wherein the second transfer driver comprises a second n-type metal oxide semiconductor transistor and a second p-type metal oxide semiconductor transistor, Wherein the second n-type metal oxide semiconductor transistor and the second p-type metal oxide semiconductor transistor are connected to the data transmission line, an Wherein the second adaptive body bias generator is configured to apply the normal body bias to the second transmission driver by: Applying a first bias voltage corresponding to a ground voltage to a body of a second n-type metal oxide semiconductor transistor, and A second bias voltage corresponding to the supply voltage is applied to the body of the second p-type metal oxide semiconductor transistor.
11. 11. The storage device of claim 6, Wherein each of the one or more non-target memory chips determines whether the corresponding on-die termination circuit is enabled based on an on-die termination signal received from the memory controller, and Wherein corresponding on-die termination circuits are included in corresponding transfer drivers of each of the one or more non-target memory chips.
12. 12. The storage device of any one of claims 1 to 11, wherein each of the plurality of memory chips comprises: a memory cell array including a plurality of non-volatile memory cells coupled to a plurality of word lines and a plurality of bit lines, the memory cell array configured to store write data and provide read data; An on-die termination circuit connected to a data transmission line configured to transmit read data and receive write data, the data transmission line being included in the channel, and A control circuit configured to control the corresponding adaptive body bias generator based on the command and address received from the memory controller and to control the on-die termination circuit based on the on-die termination signal received from the memory controller, and Wherein the plurality of memory chips are sequentially stacked on the printed circuit board in a direction perpendicular to a surface of the printed circuit board.
13. 13. The memory device of claim 12, wherein the control circuit comprises: An address comparator configured to generate an internal chip enable signal designating a target memory chip by comparing a chip address included in the address with an identifier address identifying each of the plurality of memory chips, and A control signal generator configured to generate on-die termination control signals that selectively enable the on-die termination circuits based on the on-die termination signals.
14. 14. The storage device of claim 13, wherein the address comparator is configured to: Activating an internal chip enable signal based on a chip address matching an identifier address, and The internal chip enable signal is deactivated based on the chip address being different from the identifier address.
15. 15. The memory device of claim 12, wherein the plurality of memory chips are configured to operate in a chip enable reduction mode in which the plurality of memory chips commonly receive a chip enable signal and a chip address.
16. 16. The storage device of claim 12, wherein the control circuit is configured to: selectively activating an internal chip enable signal of a designated target memory chip based on a command/address chip enable signal and a command/address received from a memory controller, and Generating an on-die termination control signal that selectively enables the on-die termination circuit based on the on-die termination signal, an Wherein the command/address includes a logical unit number address indicating a valid logical unit number.
17. 17. A storage device, comprising: Memory device, and A memory controller configured to control the memory device through the channel and select a target memory chip among the plurality of memory chips, Wherein the memory device includes a plurality of memory chips sharing a data bus for transmitting data and receiving corresponding chip select signals from the memory controller, Wherein each of the plurality of memory chips includes a memory cell array including a plurality of volatile memory cells coupled to a plurality of word lines and a plurality of bit lines, a transfer driver, and an adaptive body bias generator, the memory cell array configured to store the data, Wherein the target memory chip comprises a first adaptive body bias generator and a first transfer driver, Wherein the first adaptive body bias generator is configured to apply a first body bias to the first transmission driver based on an operation mode including a write mode or a read mode, and Wherein the target memory chip is configured to receive write data from the memory controller in the write mode and to transmit read data to the memory controller in the read mode.
18. 18. The storage device of claim 17, wherein the first adaptive body bias generator is configured to: Applying a reverse body bias to the first transfer driver in a write mode, and A normal body bias is applied to the first transfer driver in the read mode, Wherein the first transfer driver comprises a first n-type metal oxide semiconductor transistor and a first p-type metal oxide semiconductor transistor connected to the data bus, Wherein the first adaptive body bias generator is configured to apply a reverse body bias to the first transfer driver in the write mode by applying a first bias voltage less than a ground voltage to the body of the first n-type metal oxide semiconductor transistor and applying a second bias voltage greater than a supply voltage to the body of the first p-type metal oxide semiconductor transistor, and Wherein the first adaptive body bias generator is configured to apply a normal body bias to the first transfer driver in a read mode by applying a first bias voltage corresponding to a ground voltage to a body of the first n-type metal oxide semiconductor transistor and applying a second bias voltage corresponding to a power supply voltage to the body of the first p-type metal oxide semiconductor transistor.
19. 19. The storage device of claim 17 or 18, Wherein each of the one or more non-target memory chips of the plurality of memory chips not selected by the memory controller includes an on-die termination circuit connected to the data transmission line, Wherein each of the one or more non-target memory chips includes a corresponding adaptive body bias generator and a corresponding transfer driver, Wherein the corresponding adaptive body bias generator is configured to apply a second body bias to the corresponding transmit driver based on the corresponding on-die termination circuit being enabled, Wherein the one or more non-target memory chips comprise a first non-target memory chip comprising enabled first on-die termination circuitry and a second non-target memory chip comprising disabled second on-die termination circuitry, Wherein the first non-target memory chip comprises a second adaptive body bias generator and a second transfer driver, Wherein the second non-target memory chip comprises a third adaptive body bias generator and a third transfer driver, Wherein the second adaptive body bias generator is configured to apply a normal body bias to the second transmission driver, and Wherein the third adaptive body bias generator is configured to apply a reverse body bias to the third transmission driver.
20. 20. A method of operating a memory device, wherein the memory device comprises a memory device and a memory controller configured to control the memory device by communicating with the memory device via a channel, and wherein the memory device comprises a plurality of memory chips sharing the channel, the method comprising: Determining whether each of the plurality of memory chips is selected as a target memory chip based on a chip address from the memory controller; Applying, by a first adaptive body bias generator, a first body bias to a first transfer driver based on whether the mode of operation is a write mode or a read mode, the first adaptive body bias generator and the first transfer driver being included in a first memory chip selected by a memory controller as a target memory chip among the plurality of memory chips, and The second body bias is applied to the second transmit driver by a second adaptive body bias generator based on the corresponding on-die termination function, the second adaptive body bias generator and the second transmit driver being included in each of one or more non-target memory chips among the plurality of memory chips other than the first memory chip.

Description

Memory device and method of operating the same The present application claims priority from korean patent application No. 10-2024-0155842 filed in the Korean Intellectual Property Office (KIPO) on month 11 and 6 of 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field The present disclosure relates to a storage device and a method of operating a storage device. Background The memory device may include a memory device including a plurality of memory chips and a controller for controlling the memory device. In related memory systems, signal communication between a memory device and a controller may be performed at a relatively low operating frequency, as compared to signal communication in memory systems including high-speed memory, such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM). In the design and operation of memory device(s) in computing and/or mobile communication systems, as the demand for high-speed memory devices continues to rise, the integrity (or robustness) of the signals communicated between the memory devices and the controller, as well as the capacitance of the input/output pads (pads) for reducing channel power, become desirable. Disclosure of Invention Some example embodiments may provide a memory device capable of reducing capacitance of an input/output pad. Some example embodiments may provide a method of operating a memory device capable of reducing capacitance of an input/output pad. According to some example embodiments, a memory device includes a memory device and a memory controller to control the memory device through a channel. The memory device includes a plurality of memory chips sharing the channel, and the memory device selects a target memory chip among the plurality of memory chips. The target memory chip includes a first adaptive body bias generator and a first transfer driver. The first adaptive body bias generator applies a first body bias to the first transfer driver based on a mode of operation, including a write mode or a read mode. In the write mode, the target memory chip receives write data from the memory controller, and in the read mode, the target memory chip sends read data to the memory controller. According to some example embodiments, a memory device includes a memory apparatus and a memory controller to control the memory apparatus through a channel and select a target memory chip among a plurality of memory chips. The memory device includes the plurality of memory chips that share a data bus that communicates data and receive corresponding chip select signals from the memory controller. Each of the plurality of memory chips includes a memory cell array including a plurality of volatile memory cells coupled to a plurality of word lines and a plurality of bit lines, a transfer driver, and an adaptive body bias generator, and the memory cell array stores the data. The target memory chip includes a first adaptive body bias generator and a first transfer driver. The first adaptive body bias generator applies a first body bias to the first transfer driver based on a mode of operation, including a write mode or a read mode. In the write mode, the target memory chip receives write data from the memory controller, and in the read mode, the target memory chip sends read data to the memory controller. According to some example embodiments, a method of operating a storage device is provided. The memory device includes a memory device and a memory controller for controlling the memory device by communicating with the memory device via a channel, and the memory device includes a plurality of memory chips sharing the channel. According to the method, a memory chip in each of a plurality of memory chips is determined that is selected as a target memory chip based on a chip address from a memory controller, a first body bias is applied to a first transfer driver by a first adaptive body bias generator based on whether an operation mode is a write mode or a read mode, wherein the first adaptive body bias generator and the first transfer driver are included in the first memory chip in the plurality of memory chips that is selected as the target memory chip by the memory controller, and a second body bias is applied to a second transfer driver by a second adaptive body bias generator based on a corresponding on-die termination function, wherein the second adaptive body bias generator and the second transfer driver are included in each of one or more non-target memory chips in the plurality of memory chips other than the first memory chip. Thus, in a memory device and a method of operating a memory device according to example embodiments, an adaptive body bias generator in a selected chip may apply different body biases to corresponding transmission drivers based on an operation mode, and an adaptive body bias generator in an unselected chip may apply different body biases to corresponding transmission d