CN-121996156-A - Memory controller, memory system, computer device, and memory access method

CN121996156ACN 121996156 ACN121996156 ACN 121996156ACN-121996156-A

Abstract

The invention is applicable to the technical field of artificial intelligence and relates to a storage controller, a storage system, computer equipment and a storage access method. The memory controller comprises a controller chip, a random access memory chip, a second random access memory space and a third random access memory space, wherein the random access memory chip is bonded on the controller chip and adopts the same address coding rule with the controller chip, the random access memory chip comprises a first random access memory space used for storing a logic address mapping table, a second random access memory space used for storing command queues corresponding to different memory channels, each memory channel is connected with at least one memory chip, the command queues are used for caching operation commands issued to the memory chip by the controller chip, and the third random access memory space is used for storing read data returned by the memory chip in response to the operation commands or writing data required to be written by the memory chip in response to the operation commands. The invention can meet the severe requirements of a large-scale neural network model on high-bandwidth and low-delay storage access.

Inventors

LUO TING
LIN YIN
WU DAWEI
CHEN QIANG
LI FASHENG

Assignees

得一微电子股份有限公司

Dates

Publication Date: 20260508
Application Date: 20251223

Claims (10)

1. A memory controller, comprising: A controller chip; A random access memory chip bonded on the controller chip and employing the same address coding rule as the controller chip, the random access memory chip comprising: The first random access storage space is used for storing a logic address mapping table; the second random access storage space is used for storing command queues corresponding to different storage channels, each storage channel is connected with at least one storage chip, and the command queues are used for caching operation commands issued to the storage chips by the controller chip; And the third random access storage space is used for storing the read data returned by the storage chip in response to the operation command or storing the write data required to be written by the storage chip in response to the operation command.
2. The memory controller of claim 1, wherein the controller chip comprises: The request scheduling unit is used for receiving the storage access request from the computing unit, splitting the storage access request into a plurality of operation commands according to the logic address mapping table and writing the operation commands into corresponding command queues; And the channel control unit is used for acquiring the operation command from the command queue and transmitting the operation command to the memory chip for execution through the corresponding memory channel in parallel.
3. The memory controller of claim 2 further comprising an address mapping unit, the address mapping unit being adjacent to the random access memory chip, the request scheduling unit being configured to send a logical address in a memory access request to the address mapping unit, the address mapping unit being configured to query the logical address mapping table according to the logical address to obtain a corresponding physical address and return the physical address to the request scheduling unit, the request scheduling unit being configured to generate a plurality of operation commands according to the physical address and write the operation commands to a corresponding command queue.
4. The memory controller according to claim 2, wherein the request scheduling unit is further configured to, when receiving a new memory access request from the computing unit, obtain an association between the new memory access request and the memory access request, and split the new memory access request into a plurality of operation commands and write the operation commands into the corresponding command queues according to the logical address mapping table and the association.
5. The memory controller of any of claims 1-4, further comprising a mode switching unit to switch modes of operation of the random access memory chip, including a wide mode and a narrow mode, wherein a bus bit width of the random access memory chip in the wide mode coincides with a bus bit width of the controller chip, and wherein the bus bit width of the random access memory chip in the narrow mode is divided into a plurality of independent sub-channels.
6. The memory controller of any one of claims 1-4, wherein the random access memory chip is a three-dimensional stacked dynamic random access memory chip.
7. A storage system, comprising: the memory controller of any one of claims 1-6; And a plurality of memory chips connected with the memory controller through a plurality of memory channels, wherein each memory channel is connected with at least one memory chip.
8. A computer device, comprising: A calculation unit; the storage system of claim 7.
9. A memory access method suitable for a memory controller, wherein the memory controller comprises a controller chip and a random access memory chip, the random access memory chip is bonded on the controller chip and adopts the same address coding rule with the controller chip, the random access memory chip comprises a first random access memory space, a second random access memory space and a third random access memory space, and the memory access method comprises the following steps: Receiving, by the controller chip, a memory access request from a computing unit; splitting the storage access request into a plurality of operation commands through the controller chip according to a logic address mapping table stored in the first random access storage space, and writing the operation commands into command queues corresponding to different storage channels stored in the second random access storage space; And based on the third random access memory space, issuing the operation command to a connected memory chip through the memory channel by the controller chip for execution.
10. The memory access method according to claim 9, wherein the controller chip further includes a mode switching unit, the memory access method further comprising: and switching the working modes of the random access memory chip through the mode switching unit, wherein the working modes comprise a wide mode and a narrow mode, the bus bit width of the random access memory chip in the wide mode is consistent with the bus bit width of the controller chip, and the bus bit width of the random access memory chip in the narrow mode is divided into a plurality of independent sub-channels.

Description

Memory controller, memory system, computer device, and memory access method Technical Field The invention is applicable to the technical field of artificial intelligence, and particularly relates to a storage controller, a storage system, computer equipment and a storage access method. Background With the rapid development of artificial intelligence technology, the parameters and the calculation demands of a large-scale neural network model are exponentially increased. The current large-scale neural network model can generate massive random access requests in the training and reasoning process, and extremely high requirements are put on the bandwidth, delay and concurrent processing capacity of a storage system. However, conventional storage architectures have difficulty meeting the stringent requirements of large-scale neural network models for high-performance storage. Disclosure of Invention The embodiment of the invention provides a memory controller, a memory system, computer equipment and a memory access method, which can meet the severe requirements of a large-scale neural network model on high-bandwidth and low-delay memory access. In a first aspect, an embodiment of the present invention provides a memory controller, including: A controller chip; a random access memory chip bonded on the controller chip and employing the same address coding rule with the controller chip, the random access memory chip comprising: The first random access storage space is used for storing a logic address mapping table; the second random access storage space is used for storing command queues corresponding to different storage channels, each storage channel is connected with at least one storage chip, and the command queues are used for caching operation commands issued to the storage chips by the controller chip; and the third random access storage space is used for storing read data returned by the memory chip in response to the operation command or storing write data which is required to be written by the memory chip in response to the operation command. In a second aspect, an embodiment of the present invention provides a storage system, including: The embodiment of the invention provides a storage controller; and a plurality of memory chips connected with the memory controller through a plurality of memory channels, wherein each memory channel is connected with at least one memory chip. In a third aspect, an embodiment of the present invention provides a computer apparatus, including: A calculation unit; The embodiment of the invention provides a storage system. In a fourth aspect, an embodiment of the present invention provides a memory access method, applicable to a memory controller, where the memory controller includes a controller chip and a random access memory chip, the random access memory chip is bonded on the controller chip and adopts the same address coding rule with the controller chip, and the random access memory chip includes a first random access memory space, a second random access memory space, and a third random access memory space, and the memory access method includes: receiving, by the controller chip, a memory access request from the computing unit; Splitting the storage access request into a plurality of operation commands through a controller chip according to a logic address mapping table stored in the first random access storage space, and writing the operation commands into command queues corresponding to different storage channels stored in the second random access storage space; based on the third random access memory space, an operation command is issued to the connected memory chip through the memory channel by the controller chip for execution. The invention provides a new memory controller architecture, which comprises a controller chip, a random access memory chip, a second random access memory space and a third random access memory space, wherein the random access memory chip is bonded on the controller chip and adopts the same address coding rule with the controller chip, the random access memory chip comprises a first random access memory space used for storing a logic address mapping table, the second random access memory space is used for storing command queues corresponding to different memory channels, each memory channel is connected with at least one memory chip, the command queues are used for caching an operation command issued to the memory chip by the controller chip, and the third random access memory space is used for storing read data returned by the memory chip in response to the operation command or write data required to be written by the memory chip in response to the operation command. Therefore, zero copy data interaction between the controller chip and the random access memory chip is realized by tightly integrating the random access memory chip and the controller chip and sharing address codes, and the data access delay is remarkably reduced. Meanwhile, t