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CN-121996159-A - Memory capable of relieving BTI and supporting visible life management of system and method

CN121996159ACN 121996159 ACN121996159 ACN 121996159ACN-121996159-A

Abstract

The invention relates to a memory and a method capable of relieving BTI and supporting system visible life management, belonging to the field of high-reliability computing systems and memory architecture, comprising an aging-aware SRAM array supporting dual-mode operation; the system comprises an SRAM array, an aging sensing control unit, a life management module, a reconfigurable repeated delay unit, a row decoder, a readout circuit and a sensing signal output module, wherein the aging sensing control unit is connected with the SRAM array and used for detecting an aging state in real time and outputting a digital signal, the life management module is connected with the aging sensing control unit and used for receiving the digital signal and generating a configuration instruction, the reconfigurable repeated delay unit is embedded in the SRAM array and can switch modes according to the configuration instruction, the row decoder is connected with the life management module and used for receiving time sequence parameter adjustment, the readout circuit is connected with the SRAM array and the life management module and used for outputting the sensing signal, and the life management module dynamically configures the row decoder, the reconfigurable repeated delay unit and the readout circuit through closed loop feedback. The invention provides a high-performance memory system with a memory circuit architecture with anti-aging capability.

Inventors

  • HA YAJUN
  • LI YIFEI

Assignees

  • 上海科技大学

Dates

Publication Date
20260508
Application Date
20260107

Claims (10)

  1. 1. A memory that mitigates BTI and supports system visible life management, comprising: The aging sensing SRAM array supports dual-mode operation of a conventional storage mode and an aging detection mode; The aging sensing control unit is connected with the SRAM array and used for detecting the aging state of the transistor in real time and outputting a quantized digital signal; The service life management module is connected with the aging sensing control unit and is used for receiving the digital signals and dynamically generating configuration instructions; The reconfigurable repeated delay unit is embedded in the SRAM array and can be switched between a delay reference mode and a normal storage mode according to a configuration instruction; the row decoder is connected with the service life management module and used for receiving dynamic time sequence parameter adjustment; The reading circuit is connected with the SRAM array and the service life management module and is used for outputting a sensing signal; the life management module dynamically configures the row decoder, the reconfigurable repeated delay unit and the readout circuit through closed loop feedback, so as to realize system-level life management.
  2. 2. The memory capable of BTI mitigation and supporting system visible life management of claim 1, wherein the SRAM array comprises a plurality of 7T SRAM cells, each cell comprising: An inverter pair formed by cross-coupling of the first PMOS transistor PM1, the second PMOS transistor PM2, the first NMOS transistor NM1, and the second NMOS transistor NM2 for latching data; the first access transistor and the second access transistor are controlled by a word line WL and are respectively connected with a storage node Q, QB and bit lines BL and BLB; the fifth NMOS transistor NM5, controlled by the aging detection enable inversion signal ATENB, is connected in series in the feedback path of the inverter pair for shutting off the dc feedback in the aging detection mode.
  3. 3. A memory capable of BTI mitigation and supporting system visible life management in accordance with claim 2, wherein the SRAM array is reconfigured in the burn-in detection mode to: The inverter pairs of the plurality of 7T SRAM cells in the same row are disconnected from feedback through the fifth NMOS transistor NM5 and are cascaded under the action of the inter-column connection transistors controlled by the aging detection enable signal ATEN to form an inverter chain, so that the total delay monotonically increases with the aging degree of the transistors.
  4. 4. A memory capable of BTI mitigation and supporting system visible life management in accordance with claim 3, wherein the aging sense control unit comprises: a time-to-digital converter for receiving the input signal ATIN and the output signal ATOUT of the inverter chain and the analog waveform of the aging sense amplifier for measuring the delay difference; The synchronous processing circuit comprises cascaded D triggers and is used for converting delay difference into multi-bit digital code stream and outputting the multi-bit digital code stream to the service life management module.
  5. 5. A memory capable of BTI mitigation and supporting system visible life management in accordance with claim 1, wherein the reconfigurable repetition delay unit is bi-directionally coupled to the aging sensor control unit: In the aging detection mode, providing a reference delay signal to the aging sensing control unit; In the normal storage mode, data storage is engaged as a row of normal memory cells in the SRAM array.
  6. 6. The memory and method for mitigating BTI and supporting system visible life management of claim 1, further comprising: The aging sense amplifier, which shares bit lines BL, BLB with the SRAM array, comprises: a third PMOS transistor PM3 controlled by the sense enable inversion signal SAEB; The threshold voltage shift and the sensing delay degradation caused by the aging of the inverter pair PM1/PM2 and the fifth NMOS transistor NM5 are directly reflected in the output signal OUT.
  7. 7. A memory capable of alleviating BTI and supporting system visible life management according to claim 1, wherein the top of each column of the SRAM array is provided with a precharge module consisting of three PMOS transistors controlled by a precharge enable signal pre_en for potential initialization of the bit line pairs BL, BLB before each operation.
  8. 8. A method of using a memory that can alleviate BTI and support system visible life management as claimed in any one of claims 1-7, comprising the steps of: Powering up the circuit; Acquiring initial aging state data of each memory bank through an aging sensing control unit; Setting an aging threshold based on system configuration, and generating end-of-life status data; periodically observing the aging state of the memory circuit and outputting a quantized digital signal; when the aging state of the memory bank is monitored to exceed the aging threshold value, executing according to the preset working mode preference: if the preference is in the high-performance mode, the core working voltage is increased; if the preference is the maintenance function and the life mode, reconfiguring the memory control module; and cyclically executing periodic observation and dynamic regulation until the system is reset or powered off.
  9. 9. A method for mitigating BTI and supporting system visible life management according to claim 8, wherein aging state observation is achieved by: if the SRAM cell aging condition is selected as the aging standard, reconstructing the 7T SRAM cell into an inverter chain in an aging detection mode, and measuring the delay difference between the chain input ATIN and the output ATOUT; If the aging condition of the sense amplifier is selected as an aging standard, reconstructing the sense amplifier into an inverter chain in an aging detection mode, and measuring the delay difference between the input ATIN and the output ATOUT of the chain; calibrating a process bias using a reference delay signal provided by a reconfigurable repeat delay unit; The analog delay difference is converted into a multi-bit digital code stream by a time-to-digital converter as a quantized representation of the aging state.
  10. 10. The method of claim 8, wherein the core operating voltage is raised to 0.95V in the high performance mode.

Description

Memory capable of relieving BTI and supporting visible life management of system and method Technical Field The invention belongs to the field of high-reliability computing systems and memory architectures, and particularly relates to an anti-aging memory with a built-in aging sensing interface and supporting a system to dynamically implement a life management strategy. Background With the popularization of computationally intensive applications such as large language models, the reasoning process is highly dependent on KV cache to realize efficient operation. The cache is distributed in a multi-level storage hierarchy, wherein an on-chip SRAM is used as a front-end hierarchy and is responsible for processing frequent random memory accesses generated by multiple heads and layers of a model. In long-term continuous model service, KV cache is always in a high-load cycle and high-temperature state caused by the high-load cycle, and ageing and abrasion of devices are remarkably accelerated. Meanwhile, as transistor dimensions continue to enter deep nanometer dimensions, the reduced gate oxide layer and enhanced electric field further exacerbate the aging effects, making reliability a primary design goal rather than a later-in-life issue. Among the numerous aging mechanisms, bias temperature instability is one of the main reliability failure mechanisms affecting CMOS circuit performance, which manifests as an increase in transistor threshold voltage and a decrease in drain current, which in turn leads to degradation of circuit performance over operating time. Thus, the BTI affected circuits can experience significant degradation in stability and performance, which is particularly pronounced in the high-speed SRAM level in KV caches. Specifically, BTI-induced high-speed SRAM aging degradation is mainly manifested in three planes: 1. for an SRAM memory cell, the threshold voltage degradation caused by BTI can reduce the static noise margin of the SRAM memory cell and possibly cause data overturn; 2. For a sensitive amplifier, the degradation of threshold voltage and drain current caused by BTI can degrade input offset voltage and possibly cause reading errors; 3. For the control logic block, the degradation of threshold voltage caused by BTI may cause the delay of each part to increase in an unbalanced manner, which may cause timing errors. These effects are further exacerbated in environmentally demanding, long-term deployment-requiring application scenarios (e.g., high temperature and manually maintenance-limited edge servers), thereby significantly increasing the risk of system failure and maintenance costs. In view of the foregoing, there is a great need for an innovative solution that enables effective aging mitigation from the circuit bottom and provides an accurate life management interface for the upper layer system when high speed memory circuit and system designs are being addressed to BTI aging challenges. Disclosure of Invention Aiming at the problems of inaccurate aging state observation, lack of an aging state data transmission interface, limited aging relief strategy and the like of a traditional aging-resistant designed memory circuit and system, the invention provides an aging enhancement circuit and system active regulation mechanism, so that a high-performance memory system has a memory circuit architecture with aging resistance. The invention remarkably prolongs the service life of the system while keeping the high-performance operation of the memory, thereby realizing the management capability of the memory system with high reliability and long service life. The technology is suitable for application scenes such as edge computing equipment, automatic driving systems, industrial control terminals and the like which need to ensure long-term reliability in a high-intensity operation environment. In order to achieve the above object, the present invention provides a memory capable of alleviating BTI and supporting visible lifetime management of a system, comprising: The aging sensing SRAM array supports dual-mode operation of a conventional storage mode and an aging detection mode; The aging sensing control unit is connected with the SRAM array and used for detecting the aging state of the transistor in real time and outputting a quantized digital signal; The service life management module is connected with the aging sensing control unit and is used for receiving the digitized aging state signals and dynamically generating configuration instructions; The reconfigurable repeated delay unit is embedded in the SRAM array and can be switched between a delay reference mode and a normal storage mode according to a configuration instruction; the row decoder is connected with the service life management module and used for receiving dynamic time sequence parameter adjustment; The reading circuit is connected with the SRAM array and the service life management module and is used for outputting a sensing si