CN-121996161-A - Data reading method, device, electronic equipment and computer program product

CN121996161ACN 121996161 ACN121996161 ACN 121996161ACN-121996161-A

Abstract

The application provides a data reading method, a device, electronic equipment and a computer program product, wherein the method comprises the steps of executing a first data reading operation to read the first data to a buffer area at a current reading address, and executing an error correction code checking operation on the first data in the buffer area to obtain a first checking result; the method includes determining at least one candidate error bit position according to error prediction information associated with a current read address when a first check result is failed, performing an error correction attempt operation on first data according to the at least one candidate error bit position, and outputting the first data after the check is successful from a buffer when a re-performed error correction code check operation is successful. Therefore, after error correction code verification fails, the specific data bit is directly modified in an attempted mode and re-verified in the buffer zone based on pre-stored error prediction information, so that the physical re-reading operation with high delay is prevented from being immediately initiated, and the delay of data reading is remarkably reduced.

Inventors

LIN YIN
WU DAWEI
LUO TING

Assignees

深圳市硅格半导体有限公司

Dates

Publication Date: 20260508
Application Date: 20260108

Claims (10)

1. A data reading method, comprising: Executing a first data reading operation to read the first data to a buffer area at a current reading address, and executing an error correction code checking operation on the first data in the buffer area to obtain a first checking result; determining at least one candidate error bit position according to the error prediction information associated with the current read address under the condition that the first check result is failure; Performing an error correction attempt operation on the first data according to the at least one candidate error bit position, wherein the error correction attempt operation comprises performing a bit value modification operation on one or more data bits of the first data in the buffer and re-performing an error correction code verification operation on the modified first data; and outputting the first data after successful verification from the buffer area under the condition that the re-executed error correction code verification operation is successful.
2. The method of claim 1, wherein, in the event that the first check result is a failure, prior to determining at least one candidate erroneous bit location based on the erroneous prediction information associated with the current read address, the method further comprises: obtaining error data successfully corrected in historical physical rereading operation, and determining a reading address and error bit position information corresponding to the error data; And generating error prediction information related to the read address according to the read address and the error bit position information corresponding to the error data.
3. The method of claim 2, wherein the error prediction information is an error bit map, and the generating the error prediction information associated with the read address according to the read address and the error bit position information corresponding to the error data includes: collecting error bit position information corresponding to the read addresses with the same physical storage unit attribute; and generating an error bit mapping table corresponding to each physical storage unit according to the collected error bit position information, wherein at least one candidate error bit position is recorded in the error bit mapping table.
4. The method of claim 3, wherein for each physical storage unit, generating the error bit map corresponding to the physical storage unit according to the collected error bit position information includes: dividing a storage area of each physical storage unit into a plurality of subareas for each physical storage unit; Determining the historical error occurrence frequency of each bit position in each sub-area; according to the historical error occurrence frequency, determining the bit positions with the highest occurrence frequency of the first N errors of each sub-area as candidate error bit positions corresponding to the physical storage units, wherein N is more than or equal to 1 and N is a positive integer; And sequencing the candidate error bit positions corresponding to the physical storage units according to the error occurrence frequency to obtain the error bit mapping table.
5. The method of claim 1, wherein said performing an error correction attempt operation on said first data based on said at least one candidate error bit position comprises: Determining an attempt order of the at least one candidate erroneous bit location based on the erroneous prediction information; according to the try order, executing single try operation on each candidate error bit position in turn, wherein the single try operation comprises the steps of modifying the data bit corresponding to the current candidate error bit position in the buffer area, and executing error correction code check operation on the modified first data again; Ending the error correction attempting operation if the error correction code verification operation re-performed after the single attempting operation is successful; And under the condition that the error correction code verification operation re-executed after the single try operation fails, restoring the data bit corresponding to the current candidate error bit position to a state before modification, and continuing the next single try operation according to the try sequence.
6. The method according to claim 1, wherein the method further comprises: And executing a physical re-reading process after the error correction attempt operation is completed and the error correction code verification operation is not successful, wherein the physical re-reading process comprises the steps of re-reading the first data from a storage medium to the buffer area and performing error correction code verification, adjusting the reading judgment voltage of the storage medium and reading the first data from the storage medium again according to the adjusted reading judgment voltage to perform error correction code verification when the error correction code verification fails.
7. The method of any of claims 1-6, wherein the bit value modification operation comprises toggling a logical value of a data bit.
8. A data reading apparatus, comprising: the data reading module is used for executing the reading operation of the first data, reading the first data to a buffer area at the current reading address, and executing error correction code checking operation on the first data in the buffer area to obtain a first checking result; A first determining module, configured to determine at least one candidate error bit position according to the error prediction information associated with the current read address if the first check result is a failure; An error correction attempt module for performing an error correction attempt operation on the first data based on the at least one candidate error bit position, wherein the error correction attempt operation comprises performing a bit value modification operation on one or more data bits of the first data in the buffer and re-performing an error correction code verification operation on the modified first data; And the data output module is used for outputting the first data after successful verification from the buffer area under the condition that the re-executed error correction code verification operation is successful.
9. An electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the method of any one of claims 1 to 7 when the computer program is executed.
10. A computer program product, characterized in that the computer program product comprises a computer program which, when run on an electronic device, causes the electronic device to perform the method of any one of claims 1 to 7.

Description

Data reading method, device, electronic equipment and computer program product Technical Field The present application relates to the field of data storage technologies, and in particular, to a data reading method, a data reading device, an electronic device, and a computer program product. Background In a storage device (such as a solid state disk) based on a NAND flash memory, in order to ensure data reliability, an Error Correction Code (ECC) technology is generally used to perform checksum correction on read data. When memory cells develop bit errors due to aging or extended data retention time, the ECC engine attempts to correct these errors. In the related art, when the ECC engine fails to check for the first time, i.e., an uncorrectable error is reported, a conventional processing manner is to initiate a physical reread operation to the storage medium. Such operations typically require re-access to the flash media and may involve a series of hardware-level retry mechanisms to attempt to obtain the correct data. This process essentially relies on hardware to repeat operations to cope with data errors. However, each physical rereading operation involves access to the underlying storage medium, and introduces additional delay on the order of tens to hundreds of microseconds or even milliseconds, resulting in higher data read delay, which severely limits the response speed of the storage device. Disclosure of Invention The embodiment of the application provides a data reading method, a data reading device, electronic equipment and a computer program product, which can solve the problem of data reading delay reduction. A first aspect of an embodiment of the present application provides a data reading method, including performing a read operation of first data to read the first data to a buffer at a current read address, performing an error correction code check operation on the first data in the buffer to obtain a first check result, determining at least one candidate error bit position according to error prediction information associated with the current read address if the first check result is a failure, and performing an error correction attempt operation on the first data according to the at least one candidate error bit position, wherein the error correction attempt operation includes performing a bit value modification operation on one or more data bits of the first data in the buffer, and re-performing the error correction code check operation on the modified first data, and outputting the first data after the verification success from the buffer if the re-performed error correction code check operation is successful. In the technical scheme of the application, after error correction code verification fails, the specific data bit is directly subjected to trial modification and re-verification in the buffer zone based on the pre-stored error prediction information, so that the high-delay physical re-reading operation is prevented from being immediately initiated, and the delay of data reading is obviously reduced. Optionally, in a possible implementation manner of the first aspect, before determining at least one candidate error bit position according to the error prediction information associated with the current read address in the case that the first check result is a failure, the method further includes obtaining error data successfully corrected in the historical physical rereading operation, determining a read address and error bit position information corresponding to the error data, and generating the error prediction information associated with the read address according to the read address and the error bit position information corresponding to the error data. Thus, error prediction information is generated by collecting and utilizing successful error correction data in historical physical rereading, so that accurate prediction basis based on real error statistics is provided for subsequent error correction attempts. Optionally, in another possible implementation manner of the first aspect, the error prediction information is an error bit mapping table, and the generating the error prediction information associated with the read address according to the read address and the error bit position information corresponding to the error data includes collecting the error bit position information corresponding to the read address having the same physical storage unit attribute, and generating, for each physical storage unit, the error bit mapping table corresponding to the physical storage unit according to the collected error bit position information, where the error bit mapping table records at least one candidate error bit position. Therefore, the error prediction information is organized into the error bit mapping table with the physical storage unit as an index, so that the structured storage and efficient query of the error positioning information are realized, and the response speed of pr