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CN-121996168-A - Memory system and processing method of memory system

CN121996168ACN 121996168 ACN121996168 ACN 121996168ACN-121996168-A

Abstract

The application discloses a memory system and a processing method of the memory system, and belongs to the technical field of electronic equipment. The memory unit comprises a main control chip and at least two memory units, wherein each memory unit comprises a controller and a memory medium, the controller of any memory unit is connected with the controller of at least one other memory unit through a communication bus, the main control chip is respectively connected with the controllers of the memory units, the first controller is used for sending appointed type information to the second controller through the communication bus, the first controller is a controller in any memory unit, the second controller is a controller connected with the first controller in the other memory units, the appointed type information comprises information required by recovering the first memory unit, the second controller is used for writing the appointed type information into a local area, and the main control chip is used for acquiring the appointed type information stored in the second controller under the condition that the first memory unit does not respond normally.

Inventors

  • Jia Menghua

Assignees

  • 维沃移动通信有限公司

Dates

Publication Date
20260508
Application Date
20260130

Claims (10)

  1. 1. The memory system is characterized by comprising a main control chip and at least two memory units, wherein each memory unit comprises a controller and a memory medium, the controller of any memory unit is connected with the controller of at least one other memory unit through a communication bus, and the main control chip is respectively connected with the controllers of all the memory units; The first controller is a controller in any storage unit, the second controller is a controller connected with the first controller in other storage units, the specified type information comprises information required for recovering the first storage unit, and the first storage unit is a storage unit to which the first controller belongs; the second controller is used for writing the specified type information into a local area; the main control chip is used for acquiring the specified type information stored in the second controller under the condition that the first storage unit does not respond normally.
  2. 2. The system of claim 1, wherein the system further comprises a controller configured to control the controller, The main control chip is also used for sending a read command or a write command to the first storage unit; the main control chip is specifically configured to send an information acquisition request to the second controller when the first storage unit does not respond to the read command or the write command; The second controller is further configured to output the specified type of information to the main control chip in response to the information acquisition request.
  3. 3. The system of claim 1, wherein the specified category information comprises address mapping table information for data in a storage medium, the storage medium comprising an external debug interface; the main control chip is further configured to output the address mapping table information and a data recovery prompt, where the data recovery prompt is used to instruct that data in the storage medium is read out according to the address mapping table information through an external debug pin of the storage medium in the first storage unit.
  4. 4. A system according to claim 3, wherein the address mapping table information comprises a starting address and a size of an address mapping table; and under the condition that the external equipment is connected with an external debugging pin of the storage medium, the external equipment is used for reading an address mapping table of the storage medium according to the starting address and the size, and reading data from the storage medium based on the storage address recorded in the address mapping table.
  5. 5. The system of claim 3, wherein the specified category information further comprises hardware index information and log information; The main control chip is further used for writing control software into the first controller again under the condition that the log information characterizes that the software is abnormal so as to recover the software; The main control chip is further specifically configured to output the address mapping table information and the data recovery prompt when the hardware index represented by the hardware index information is abnormal.
  6. 6. The system according to any one of claims 1 to 5, wherein a correspondence between a register address and an information type is stored in the first controller, the register address being an address of a backup register in the second controller, the specified type information including information of the information type; the first controller is specifically configured to sequentially send each register address and information corresponding to the register address to the second controller according to a recording sequence of the register addresses in the corresponding relationship; the second controller is specifically configured to sequentially write information corresponding to the information types of the register addresses into the register addresses.
  7. 7. The system of claim 6, wherein the first controller is further specifically configured to: Determining the number i of the register addresses which are currently transmitted, and transmitting the (i+1) th register address and information to be transmitted in the corresponding relation to the second controller, wherein the information to be transmitted is information of the information type corresponding to the (i+1) th register address; And adding 1to the number i of the register addresses, and continuously sending the (i+1) th register address and information to be sent in the corresponding relation to the second controller under the condition that the second controller finishes writing until the i is equal to the total number of the addresses.
  8. 8. The system of claim 7, wherein the first controller comprises a first communication interface and a first control unit, and the second controller comprises a second communication interface and a second control unit; The first control unit is configured to send the (i+1) th register address and the information to be sent to the first communication interface; The first communication interface is configured to send the i+1st register address and the information to be sent to the second communication interface through the communication bus; the second communication interface is configured to send the i+1st register address and the information to be sent, which are received each time, to the second control unit; The second control unit is configured to write the information to be sent into the (i+1) th register address.
  9. 9. The system of any of claims 1-5, wherein the controllers of each two of the memory units are connected by a communication bus, and wherein the controllers of each two of the memory units are arranged adjacently.
  10. 10. A method of processing a memory system, as applied to the system of any of claims 1-9, the method comprising: The method comprises the steps that a first controller sends specified type information to a second controller through a communication bus, wherein the first controller is a controller in any storage unit, the second controller is a controller connected with the first controller in other storage units, the specified type information comprises information required by recovering the first storage unit, and the first storage unit is a storage unit to which the first controller belongs; Writing, by the second controller, the specified category information locally; and acquiring the specified type information stored in the second controller by the main control chip under the condition that the first storage unit does not respond normally.

Description

Memory system and processing method of memory system Technical Field The application belongs to the technical field of electronic equipment, and particularly relates to a memory system and a processing method of the memory system. Background In order to meet the high-speed requirement, a plurality of storage units are arranged in the memory system, wherein each storage unit comprises a controller and a storage medium, and the controller in each storage unit responds to a command of a requester to perform data access on the storage medium. In the related art, the storage units are independent from each other, and when one storage unit fails, the data of the storage medium in the storage unit cannot be accessed, so that the problem of data loss occurs. Disclosure of Invention The embodiment of the application aims to provide a memory system and a processing method of the memory system, which can solve the problem of data loss. In a first aspect, an embodiment of the present application provides a memory system, including a main control chip and at least two memory units, where each memory unit includes a controller and a storage medium, the controller of any one memory unit is connected with the controllers of at least one other memory unit through a communication bus, and the main control chip is respectively connected with the controllers of the memory units; The first controller is a controller in any storage unit, the second controller is a controller connected with the first controller in other storage units, the specified type information comprises information required for recovering the first storage unit, and the first storage unit is a storage unit to which the first controller belongs; the second controller is used for writing the specified type information into a local area; the main control chip is used for acquiring the specified type information stored in the second controller under the condition that the first storage unit does not respond normally. In a second aspect, an embodiment of the present application provides a processing method of a memory system, applied to the memory system of the first aspect, where the method includes: The method comprises the steps that a first controller sends specified type information to a second controller through a communication bus, wherein the first controller is a controller in any storage unit, the second controller is a controller connected with the first controller in other storage units, the specified type information comprises information required by recovering the first storage unit, and the first storage unit is a storage unit to which the first controller belongs; Writing, by the second controller, the specified category information locally; and acquiring the specified type information stored in the second controller by the main control chip under the condition that the first storage unit does not respond normally. In a third aspect, an embodiment of the present application provides an electronic device, including a processor and the above memory system, where the memory system stores a program or instructions executable on the processor, and the program or instructions implement steps of a processing method of the above memory system when executed by the processor. In a fourth aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which, when executed by a processor, implement the steps of the processing method of the memory system described above. In a fifth aspect, an embodiment of the present application provides a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and the processor is configured to execute a program or instructions to implement the steps of the processing method of the memory system. In a seventh aspect, embodiments of the present application provide a computer program product stored in a storage medium, the program product being executed by at least one processor to implement the steps of the processing method of the memory system described above. In the embodiment of the application, the main control chip is respectively connected with the controllers of the storage units, and the communication bus is set to establish connection between the controllers of the storage units, so that the controllers of the storage units can communicate with each other. The first controller sends the appointed type information to the second controller through the communication bus, and the second controller writes the appointed type information into the local area to realize backup. And under the condition that the storage unit to which the first controller belongs does not respond normally, the main control chip acquires the appointed type information stored in the second controller. Because the information required by the specified type information for recovering the first storage unit