CN-121996169-A - Input/output IO address processing method and device and electronic equipment

Abstract

The application discloses a processing method and device of an input/output IO address and electronic equipment, and belongs to the technical field of data storage. The method comprises the steps of obtaining IO addresses of a plurality of first IO requests aiming at a target application, carrying out aggregation treatment on the IO addresses of the plurality of first IO requests to obtain an aggregated first IO address set and a discrete second IO address set, preloading IO data corresponding to each IO address in the first IO address set into a first area of a memory, and preloading IO data corresponding to each IO address in the second IO address set into a second area of the memory under the condition that the target application is started.

Inventors

• Zhu Hancong
• ZHANG TENG

Assignees

• 维沃移动通信有限公司

Dates

Publication Date

20260508

Application Date

20260130

Claims (10)

1. 1. The processing method of the input/output IO address is characterized by comprising the following steps: Acquiring IO addresses of a plurality of first IO requests aiming at a target application, and carrying out aggregation treatment on the IO addresses of the plurality of first IO requests to obtain an aggregated first IO address set and a discrete second IO address set; And under the condition that the target application is started, preloading the IO data corresponding to each IO address in the first IO address set into a first area of a memory, and preloading the IO data corresponding to each IO address in the second IO address set into a second area of the memory.
2. 2. The method of claim 1, wherein preloading the IO data corresponding to each IO address in the first set of IO addresses into the first region of memory comprises: And under the condition that a second IO request aiming at the target application is detected, if the second IO request comprises at least one IO address in the first IO address set, preloading IO data corresponding to each IO address in the first IO address set into a first area of the memory.
3. 3. The method of claim 1, wherein preloading the IO data corresponding to each IO address in the second set of IO addresses into the second region of the memory comprises: And sequentially preloading IO data corresponding to each IO address in the second IO address set into a second area of the memory according to the priority order of threads to which the IO addresses belong.
4. 4. The method of claim 1, wherein after preloading the IO data corresponding to each IO address in the second set of IO addresses into the second region of the memory, the method further comprises: And performing memory curing processing on IO data corresponding to the preloaded IO address in the second area of the memory.
5. 5. The method of claim 1, wherein aggregating the IO addresses of the plurality of first IO requests to obtain an aggregated first set of IO addresses and a discrete second set of IO addresses, comprises: Inputting the IO addresses of the plurality of first IO requests into an IO address aggregation model, executing a multi-stage segmentation algorithm and judging aggregation conditions on the basis of aggregation parameters in the IO address aggregation model, determining an IO address set which meets the aggregation conditions after segmentation as a first IO address set, and determining an IO address set which does not meet the aggregation conditions after segmentation as a discrete second IO address set.
6. 6. The method of claim 5, wherein the method further comprises: Calculating at least one data of a preload access hit rate, a preload access miss rate, a preload memory efficiency ratio, a preload request decrement amount, and a preload delay decrement amount based on the IO data corresponding to the plurality of first IO requests for the target application; Updating aggregation parameters in the IO address aggregation model based on at least one data of the preload access hit rate, the preload access miss rate, the preload memory efficiency ratio, the preload request reduction amount, the preload delay reduction amount; the preloading access hit rate characterizes the ratio of the number of times that a third IO request initiated by the target application hits IO data preloaded into the memory to the total number of times of the third IO request under the condition that IO data corresponding to the first IO request is preloaded into the memory; the preloading access non-hit rate characterizes the ratio of the number of times that a third IO request initiated by the target application misses IO data preloaded into the memory to the total number of times of the third IO request under the condition that IO data corresponding to the first IO request is preloaded into the memory; The pre-loaded memory efficiency ratio represents the ratio of a first memory occupation amount to a second memory occupation amount, wherein the first memory occupation amount represents the memory occupation amount when the IO data corresponding to the first IO request is not pre-loaded; The method comprises the steps of obtaining a preloading request reduction amount, wherein the preloading request reduction amount represents a difference value between a first IO request number and a second IO request number, the first IO request number represents the number of first IO requests initiated by a target application under the condition that IO data corresponding to the first IO request is not preloaded to a memory, and the second IO request number represents the number of first IO requests initiated by the target application under the condition that IO data corresponding to the first IO requests are preloaded to the memory; The pre-load delay reduction amount represents a difference value between a first IO operation time and a second IO operation time, the first IO operation time represents a time interval from a first IO request initiation time of the target application to loading of IO data corresponding to the first IO request into the memory when IO data corresponding to the first IO request is not pre-loaded into the memory, and the second IO operation time represents a time interval from the first IO request initiation time of the target application to loading of IO data corresponding to the first IO request into the memory when IO data corresponding to the first IO request is pre-loaded into the memory.
7. 7. A processing apparatus for inputting/outputting an IO address, comprising: the processing module is used for acquiring the IO addresses of a plurality of first IO requests aiming at the target application, and carrying out aggregation processing on the IO addresses of the plurality of first IO requests to obtain an aggregated first IO address set and a discrete second IO address set; The preloading module is used for preloading the IO data corresponding to each IO address in the first IO address set into a first area of a memory and preloading the IO data corresponding to each IO address in the second IO address set into a second area of the memory under the condition that the target application is started.
8. 8. An electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the method of processing an input output IO address as claimed in any one of claims 1 to 6.
9. 9. A readable storage medium, wherein a program or instructions are stored on the readable storage medium, which when executed by a processor, implement the steps of the method for processing an input-output IO address according to any one of claims 1-6.
10. 10. A chip comprising a processor and a communication interface, the communication interface and the processor being coupled, the processor being configured to execute a program or instructions to implement the steps of the method for processing an input/output IO address according to any one of claims 1-6.

Description

Input/output IO address processing method and device and electronic equipment Technical Field The application belongs to the technical field of data storage, and particularly relates to a processing method and device of an input/output IO address and electronic equipment. Background In daily use of electronic equipment, system fluency is a vital user experience index, and a very bad experience can be brought to a user by a stuck frame drop of an operation interface. Through analyzing a large amount of user stuck data, it is found that the user interface stuck caused by the Input/Output (IO) problem is about 22%, that is, the data is not in the memory, and an IO request needs to be initiated to read the data into the memory. Therefore, the blocking caused by the IO problem is optimized, and the fluency of the user in the process of using the electronic equipment can be improved. Currently, the mainstream of electronic devices uses a universal flash memory storage (Universal Flash Storage, UFS) protocol, and through iterative upgrade of the UFS protocol, the read-write bandwidth of the electronic devices is increased and the IO access delay is shortened. The theoretical bandwidths of the past UFS protocol standards are shown in table 1. TABLE 1 Besides improving IO capacity through protocol upgrading, the IO capacity can be further enhanced through increasing hardware redundancy, for example, two UFS4.0 chips are packaged and read and written in a mode of a redundant array of independent disks (Redundant Array of INDEPENDENT DISKS, RAID), so that theoretical bandwidth is doubled, and hardware IO capacity is further enhanced. However, the above solution has the following drawbacks: The blocking of a large number of user scenes is not caused by insufficient hardware capability of the UFS device, but rather, the increase of hardware redundancy increases the cost of the electronic device, for example, in the page sliding process of typical applications (such as instant messaging applications), the number of concurrent IO requests generated by the electronic device is lower than the upper limit of parallel processing of a single UFS 4.0 device, and the required read-write bandwidth is far less than the interface capability of the single UFS 4.0 device. Therefore, in such a scenario, the performance improvement due to hardware redundancy cannot be effectively utilized, belonging to the performance excess; second, neglecting the locality principle underlying the user context IO access logical block address (Logical Block Address, LBA), hardware bandwidth stacking does not solve the problem of stuck. Disclosure of Invention The embodiment of the application aims to provide a processing method and device for input/output (IO) addresses and electronic equipment, and the smoothness of a system can be improved without increasing the hardware cost of UFS equipment. In a first aspect, an embodiment of the present application provides a method for processing an input/output IO address, including: Acquiring IO addresses of a plurality of first IO requests aiming at a target application, and carrying out aggregation treatment on the IO addresses of the plurality of first IO requests to obtain an aggregated first IO address set and a discrete second IO address set; And under the condition that the target application is started, preloading the IO data corresponding to each IO address in the first IO address set into a first area of a memory, and preloading the IO data corresponding to each IO address in the second IO address set into a second area of the memory. In a second aspect, an embodiment of the present application provides a processing apparatus for an input/output IO address, including: the processing module is used for acquiring the IO addresses of a plurality of first IO requests aiming at the target application, and carrying out aggregation processing on the IO addresses of the plurality of first IO requests to obtain an aggregated first IO address set and a discrete second IO address set; The preloading module is used for preloading the IO data corresponding to each IO address in the first IO address set into a first area of a memory and preloading the IO data corresponding to each IO address in the second IO address set into a second area of the memory under the condition that the target application is started. In a third aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the method as described in the first aspect. In a fourth aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which when executed by a processor perform the steps of the method according to the first aspect. In a fifth aspect, an embodiment of the present application provides a chip, whe