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CN-121996173-A - Storage device

CN121996173ACN 121996173 ACN121996173 ACN 121996173ACN-121996173-A

Abstract

Embodiments of the present invention relate to a storage device. The computer system of the embodiment transmits a write request to the storage device, the write request specifying a1 st logical address for identifying 1 st data to be written and a length of the 1 st data. The computer system receives a1 st physical address from the storage device, and the 1 st logical address, the 1 st physical address representing both a1 st block selected by the storage device from blocks other than bad blocks as a write target block for the 1 st data, and a1 st physical storage location within the 1 st block in which the 1 st data is written. The computer system maps the 1 st physical address to the 1 st logical address in a1 st table that manages a mapping between logical addresses and physical addresses of the storage device.

Inventors

  • SUGANO SHINICHI

Assignees

  • 铠侠股份有限公司

Dates

Publication Date
20260508
Application Date
20180806
Priority Date
20171030

Claims (10)

  1. 1.A storage device, comprising: a control circuit connectable to the host device, and A plurality of nonvolatile memory chips including a plurality of memory blocks, respectively The control circuit is configured to: Receiving a write request and 1 st data to be written from the host device, the write request specifying a1 st logical address corresponding to the 1 st data and a length of the 1 st data; selecting a1 st writable memory block from the plurality of memory blocks of one of the plurality of non-volatile memory chips as a write target block for the 1 st data in response to receiving the write request and writing the 1 st data to a1 st physical storage location within the 1 st writable memory block, and The 1 st logical address and 1 st physical address are sent to the host device, the 1 st physical address representing both the 1 st writable memory block and the 1 st physical storage location to update a mapping between logical addresses and physical addresses of the storage device by the host device.
  2. 2. The storage device of claim 1, wherein The control circuit is further configured to: A read request is received from the host device, the read request specifying the 1 st physical address to which the 1 st logical address has been mapped by the host device.
  3. 3. The storage device of claim 1, wherein The control circuit is further configured to: Copying the 1 st data from the old physical storage location to the new physical storage location, and Transmitting the 1 st logical address, a2 nd physical address representing the old physical storage location, and a 3 rd physical address representing the new physical storage location to the host device; the host device is configured to: Acquiring a current physical address mapped to the 1 st logical address; updating the mapping when the 2 nd physical address is consistent with the acquired current physical address such that the 3 rd physical address is mapped to the 1 st logical address, and When the 2 nd physical address is inconsistent with the acquired current physical address, the mapping is not updated and the current physical address is maintained.
  4. 4. The storage device of claim 3, wherein The control circuit is further configured to invalidate data corresponding to the 2 nd physical address in response to receiving a1 st instruction designating the 2 nd physical address from the host device.
  5. 5. The storage device of claim 1, wherein When the 1 st data is update data of old data that has been written to the storage device, the control circuit is further configured to invalidate the old data in response to receiving a1 st instruction from the host device specifying a physical address corresponding to the old data.
  6. 6. The storage device of claim 1, wherein When the 1 st data is update data of old data that has been written to the storage device and the old data is duplicate data referred to by a plurality of logical addresses, the control circuit is further configured to reduce a reference count indicating the number of logical addresses referred to the old data in response to receiving from the host device a1 st instruction designating a physical address corresponding to the old data.
  7. 7. The storage device of claim 6, wherein The host device does not save the reference count.
  8. 8. A storage device, comprising: a control circuit connectable to the host device, and A plurality of nonvolatile memory chips including a plurality of memory blocks, respectively The control circuit is configured to: receiving a read request from the host device for 1 st data written to a1 st physical storage location of a1 st memory block of the plurality of memory blocks of one of the plurality of nonvolatile memory chips, the read request specifying a1 st physical address representing both the 1 st memory block and the 1 st physical storage location; Transmitting the 1 st data to the host device without performing logical-to-physical address conversion at the time of reading the 1 st data in response to receiving the read request designating the 1 st physical address; Copying the 1 st data from the old physical storage location to the new physical storage location, and A1 st logical address corresponding to the 1 st data, a2 nd physical address indicating the old physical storage location, and a 3 rd physical address indicating the new physical storage location are transmitted to the host device.
  9. 9. The storage device of claim 8, wherein The host device is configured to: acquiring a current physical address mapped to the 1 st logical address sent from the control circuit; updating the mapping such that the 3 rd physical address maps to the 1 st logical address when the 2 nd physical address coincides with the acquired current physical address, and When the 2 nd physical address is inconsistent with the acquired current physical address, the mapping is not updated and the current physical address is maintained.
  10. 10. The storage device of claim 8, wherein The control circuit is further configured to invalidate data corresponding to the 2 nd physical address in response to receiving a1 st instruction designating the 2 nd physical address from the host device.

Description

Storage device Information about the divisional application The scheme is a divisional application. The parent case of the division is an invention patent application with the application date of 2018, 8, 6, 201810887535.3 and the name of a control method of a computer system and a storage device. [ Related application ] The present application enjoys priority of Japanese patent application No. 2017-209344 (application date: 10/30/2017). The present application includes the entire content of the basic application by referring to the basic application. Technical Field Embodiments of the present invention relate to a control method of a computer system and a storage device (storage device). Background In recent years, storage devices including nonvolatile memories have been widely used. As one of such storage devices, a Solid State Disk (SSD) based on NAND (Not And) flash memory technology is known. In a storage device used in a computer system such as a server in a data center, high I/O (Input/Output) performance is required. Therefore, recently, a new interface between the host side and the storage device side is started to be proposed. However, if the number of defective blocks included in the nonvolatile memory increases, there is a case where the amount of replacement information for replacing the defective blocks with other blocks increases on the storage device side, and the read delay time increases due to the replacement processing. This sometimes becomes a factor in degrading the I/O performance of the system as a whole. Disclosure of Invention Embodiments of the present invention provide a computer system and a control method capable of improving I/O performance. According to an embodiment, a computer system for controlling a storage device including a plurality of nonvolatile memory chips (nonvolatile memory die) each including a plurality of blocks and a controller includes a memory, and a processor configured to be electrically connected to the memory and execute a computer program stored in the memory. The processor sends a write request to the storage specifying a1 st logical address identifying 1 st data to be written and a length of the 1 st data. The processor receives a1 st physical address from the storage device, the 1 st physical address representing both a1 st block selected by the storage device from blocks other than bad blocks as a write target block for the 1 st data, and a1 st physical storage location within the 1 st block to which the 1 st data is written, and the 1 st logical address. The processor maps the 1 st physical address to the 1 st logical address in a1 st table that manages mappings between logical addresses and physical addresses of the storage device. Drawings Fig. 1 is a block diagram showing a relationship between a host and a memory system (flash storage device). Fig. 2 is a diagram for explaining the function sharing between the flash memory device and the host. Fig. 3 is a block diagram showing an exemplary configuration of the flash memory device. Fig. 4 is a diagram showing an instruction for the In-Drive-GC API. Fig. 5 is a diagram showing an instruction for the superblock API. Fig. 6 is a block diagram showing a relationship between a flash I/O control circuit provided in a flash memory device and a plurality of NAND-type flash memory chips. Fig. 7 is a diagram showing a configuration example of a superblock (parallel unit) constructed from a set of a plurality of blocks. Fig. 8 is a diagram for explaining a relationship between a block address of a super block and block addresses of respective blocks constituting the super block. Fig. 9 is a diagram for explaining an operation of replacing each defective block belonging to a certain nonvolatile memory chip with another block of the nonvolatile memory chip. Fig. 10 is a diagram for explaining an operation of selecting a write target block from among non-defective blocks in a super block without replacing the defective block. Fig. 11 is a diagram for explaining a write instruction applied to the flash memory device. Fig. 12 is a diagram for explaining a response to the write command of fig. 11. Fig. 13 is a diagram for explaining Trim instructions applied to a flash memory device. Fig. 14 is a diagram showing an operation of writing data to a superblock having a defective block. Fig. 15 is a diagram showing an example of the structure of the physical address included in the response of fig. 12. Fig. 16 is a diagram showing a relationship between a block address of a super block and block addresses of blocks included in the super block. Fig. 17 is a diagram for explaining an operation of writing a pair of logical addresses and data to a page within a block. Fig. 18 is a diagram for explaining an operation of writing data to a user data area of a page within a block and writing a logical address of the data to a redundant area of the page. Fig. 19 is a diagram for explaining an operation of writing a plurality