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CN-121996174-A - Memory system

CN121996174ACN 121996174 ACN121996174 ACN 121996174ACN-121996174-A

Abstract

Embodiments of the invention relate to a memory system. The computer system of the embodiment transmits a write request to the storage device, the write request specifying a1 st logical address for identifying 1 st data to be written and a length of the 1 st data. The computer system receives a1 st physical address from the storage device, and the 1 st logical address, the 1 st physical address representing both a1 st block selected by the storage device from blocks other than bad blocks as a write target block for the 1 st data, and a1 st physical storage location within the 1 st block in which the 1 st data is written. The computer system maps the 1 st physical address to the 1 st logical address in a1 st table that manages a mapping between logical addresses and physical addresses of the storage device.

Inventors

  • SUGANO SHINICHI

Assignees

  • 铠侠股份有限公司

Dates

Publication Date
20260508
Application Date
20180806
Priority Date
20171030

Claims (12)

  1. 1. A memory system capable of being connected to a host, comprising: a nonvolatile memory including a plurality of blocks each being a unit of a data deleting action, and And a controller electrically connected to the nonvolatile memory and configured to: Managing a plurality of block groups, each of the plurality of block groups including at least one of the plurality of blocks, and A write instruction is received from the host in response to requesting writing of the 1 st data and specifying an identifier associated with a write destination chunk to which the 1 st data should be written: selecting a block group corresponding to the specified identifier from the plurality of block groups based on the specified identifier, Selecting a1 st block from the at least one of the plurality of blocks included in the selected block group, and Writing the 1 st data into the 1 st position of the 1 st block.
  2. 2. The memory system of claim 1, wherein The controller is further configured to notify the host of a1 st logical address associated with the 1 st data.
  3. 3. The memory system of claim 1, wherein The write instruction also specifies a 1 st logical address associated with the 1 st data, but does not specify an identifier of the 1 st block.
  4. 4. The memory system of claim 1, wherein The controller is further configured to notify the host of the 1 st location by using at least the identifier of the 1 st block.
  5. 5. The memory system of claim 4, wherein The controller is configured to notify the host of the 1 st position by using an offset address in the 1 st block and the identifier of the 1 st block.
  6. 6. The memory system of claim 5, wherein The plurality of blocks each including a plurality of pages, each of the plurality of pages being a unit of a write action, and The controller is configured to specify the offset address by using a multiple of a granularity having a size different from a size of each of the plurality of pages.
  7. 7. The memory system of claim 1, wherein Each of the plurality of blocks belongs to only one block group of the plurality of block groups.
  8. 8. The memory system of claim 1, wherein The controller is further configured to: copying the 2 nd data from the 1 st block to the 2 nd block of the plurality of blocks, and Notifying the host of at least a 2 nd logical address associated with the 2 nd data.
  9. 9. The memory system of claim 8, wherein The controller is further configured to notify the host of the identifier of the 2 nd block.
  10. 10. The memory system of claim 8, wherein The 2 nd block is included in the block group including the 1 st block.
  11. 11. The memory system of claim 8, wherein The 2 nd block is included in a block group different from the block group including the 1 st block.
  12. 12. A memory system capable of being connected to a host, comprising: a nonvolatile memory including a plurality of blocks each being a unit of a data deleting action, and And a controller electrically connected to the nonvolatile memory and configured to: In response to receiving a write instruction requesting writing of 1 st data from the host, designating a logical address corresponding to the 1 st data and not designating an identifier of a block to which the 1 st data should be written, writing the 1 st data to a1 st storage location in the nonvolatile memory, and notifying the host of the 1 st storage location using the identifier of the block to which the 1 st data has been written and an offset address within the block to which the 1 st data has been written, and The 1 st data is read from the 1 st storage location in the nonvolatile memory in response to receiving a read instruction from the host requesting the 1 st data be read and specifying the identifier of the block to which the 1 st data has been written and the offset address within the block to which the 1 st data has been written.

Description

Memory system Information about the divisional application The scheme is a divisional application. The parent case of the division is an invention patent application with the application date of 2018, 8, 6, 201810887535.3 and the name of a control method of a computer system and a storage device. [ Related application ] The present application enjoys priority of Japanese patent application No. 2017-209344 (application date: 10/30/2017). The present application includes the entire content of the basic application by referring to the basic application. Technical Field Embodiments of the present invention relate to a control method of a computer system and a storage device (storage device). Background In recent years, storage devices including nonvolatile memories have been widely used. As one of such storage devices, a Solid State Disk (SSD) based on NAND (Not And) flash memory technology is known. In a storage device used in a computer system such as a server in a data center, high I/O (Input/Output) performance is required. Therefore, recently, a new interface between the host side and the storage device side is started to be proposed. However, if the number of defective blocks included in the nonvolatile memory increases, there is a case where the amount of replacement information for replacing the defective blocks with other blocks increases on the storage device side, and the read delay time increases due to the replacement processing. This sometimes becomes a factor in degrading the I/O performance of the system as a whole. Disclosure of Invention Embodiments of the present invention provide a computer system and a control method capable of improving I/O performance. According to an embodiment, a computer system for controlling a storage device including a plurality of nonvolatile memory chips (nonvolatile memory die) each including a plurality of blocks and a controller includes a memory, and a processor configured to be electrically connected to the memory and execute a computer program stored in the memory. The processor sends a write request to the storage specifying a1 st logical address identifying 1 st data to be written and a length of the 1 st data. The processor receives a1 st physical address from the storage device, the 1 st physical address representing both a1 st block selected by the storage device from blocks other than bad blocks as a write target block for the 1 st data, and a1 st physical storage location within the 1 st block to which the 1 st data is written, and the 1 st logical address. The processor maps the 1 st physical address to the 1 st logical address in a1 st table that manages mappings between logical addresses and physical addresses of the storage device. Drawings Fig. 1 is a block diagram showing a relationship between a host and a memory system (flash storage device). Fig. 2 is a diagram for explaining the function sharing between the flash memory device and the host. Fig. 3 is a block diagram showing an exemplary configuration of the flash memory device. Fig. 4 is a diagram showing an instruction for the In-Drive-GC API. Fig. 5 is a diagram showing an instruction for the superblock API. Fig. 6 is a block diagram showing a relationship between a flash I/O control circuit provided in a flash memory device and a plurality of NAND-type flash memory chips. Fig. 7 is a diagram showing a configuration example of a superblock (parallel unit) constructed from a set of a plurality of blocks. Fig. 8 is a diagram for explaining a relationship between a block address of a super block and block addresses of respective blocks constituting the super block. Fig. 9 is a diagram for explaining an operation of replacing each defective block belonging to a certain nonvolatile memory chip with another block of the nonvolatile memory chip. Fig. 10 is a diagram for explaining an operation of selecting a write target block from among non-defective blocks in a super block without replacing the defective block. Fig. 11 is a diagram for explaining a write instruction applied to the flash memory device. Fig. 12 is a diagram for explaining a response to the write command of fig. 11. Fig. 13 is a diagram for explaining Trim instructions applied to a flash memory device. Fig. 14 is a diagram showing an operation of writing data to a superblock having a defective block. Fig. 15 is a diagram showing an example of the structure of the physical address included in the response of fig. 12. Fig. 16 is a diagram showing a relationship between a block address of a super block and block addresses of blocks included in the super block. Fig. 17 is a diagram for explaining an operation of writing a pair of logical addresses and data to a page within a block. Fig. 18 is a diagram for explaining an operation of writing data to a user data area of a page within a block and writing a logical address of the data to a redundant area of the page. Fig. 19 is a diagram for explaining an operation of writing a plurality