CN-121996249-A - Compiling method, compiling device, electronic equipment and storage medium

CN121996249ACN 121996249 ACN121996249 ACN 121996249ACN-121996249-A

Abstract

The embodiment of the invention provides a compiling method, a compiling device, electronic equipment and a storage medium, and belongs to the technical field of computer compiling. The corresponding method comprises the steps of mapping operator nodes of a predetermined target application to a virtual processing unit, generating a PE array according to a plurality of virtual processing units, wherein the PE array is used for representing data dependency relations among the operator nodes executed by the virtual processing unit, corresponding execution clock periods, hardware functional units supported by the virtual processing unit and a plurality of operator nodes, and generating hardware description language codes of the target application according to the PE array. The invention can perform one-time and collaborative global optimization on the target software and the bottom reconfigurable hardware architecture, thereby efficiently and automatically generating the customized computing system with high performance and high energy efficiency.

Inventors

ZHU JIANFENG
ZHU QINGYU
LIU LEIBO

Assignees

清华大学

Dates

Publication Date: 20260508
Application Date: 20251230

Claims (10)

1. A compiling method, comprising: Mapping operator nodes of a predetermined target application to a virtual processing unit; generating a PE array according to a plurality of virtual processing units, wherein the PE array is used for representing the operator nodes executed by the virtual processing units, corresponding execution clock periods, hardware functional units supported by the virtual processing units and data dependency relations among the operator nodes; And generating the hardware description language code of the target application according to the PE array.
2. The compiling method of claim 1, wherein generating hardware description language code of the target application from the PE array comprises: Generating a first constraint condition according to the number of the hardware functional units required by the PE array and the number of physical connection units among a plurality of virtual processing units; Generating a first intermediate representation of the target application according to the first constraint condition and the PE array; generating a second constraint condition according to the number of registers required by the PE array; generating a second intermediate representation of the target application according to the second constraint condition and the first intermediate representation; generating the hardware description language code according to the second intermediate representation.
3. The compiling method of claim 2, wherein the first intermediate representation comprises a structure of the PE array, a mapping relationship between the operator nodes and the virtual processing units, and a data dependency relationship between a plurality of virtual processing units, wherein the data dependency relationship between the plurality of virtual processing units is determined by the data dependency relationship between the plurality of operator nodes.
4. The compilation method according to claim 2, wherein the second intermediate representation comprises a configuration of all hardware functional units, ports, sources and registers of input data of the virtual processing unit.
5. The compiling method of claim 2, wherein generating the first constraint according to the number of the hardware functional units required by the PE array and the number of physical connection units between the plurality of virtual processing units comprises: And optimizing the number of the hardware functional units required by the PE array and the number of the physical connection units among the plurality of virtual processing units to be minimum through a pre-generated integer programming model, and generating the first constraint condition.
6. The compiling method of claim 2, wherein generating the second constraint according to the number of registers required by the PE array comprises: Merging the registers, which are not in conflict with the use time, in the first intermediate representation through a pre-generated graph coloring model to generate a second constraint condition; the step of determining the operator node of the target application comprises the following steps: Determining a data flow diagram of the target application according to the execution logic of the target application; And determining the operator node according to the data flow graph.
7. A compiling apparatus, comprising: The node mapping module is used for mapping operator nodes of the predetermined target application to the virtual processing unit; The PE array generation module is used for generating a PE array according to a plurality of the virtual processing units, wherein the PE array is used for representing the operator nodes executed by the virtual processing units, corresponding execution clock periods, hardware functional units supported by the virtual processing units and data dependency relations among the operator nodes; And the hardware code generation module is used for generating the hardware description language code of the target application according to the PE array.
8. A computer program product comprising computer programs/instructions which, when executed by a processor, implement the steps of the compiling method of any one of claims 1 to 6.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the compiling method according to any one of claims 1 to 6 when the program is executed by the processor.
10. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the compiling method according to any one of claims 1 to 6.

Description

Compiling method, compiling device, electronic equipment and storage medium Technical Field The application belongs to the technical field of computers, and particularly relates to a compiling method, a compiling device, electronic equipment and a storage medium. Background Currently, emerging applications are continuously emerging, user demands are continuously increased, and the skill ability of the departments is rapidly developed, so that software is updated more and more rapidly, and as a result, the hardware implementation form cannot adapt to software changes, and thus, the hardware production is difficult to have a too short life cycle and a too high one-time engineering cost. In the prior art, a reconfigurable computing architecture (such as coarse-grained reconfigurable array, coarse Grained Reconfigurable Array, CGRA) oriented to a specific field has become an important solution to solve the above-mentioned problems. The design core of such architecture is how to automatically generate a hardware structure and its configuration information that is highly optimized in terms of energy efficiency and area based on a set of target software applications (kernels). Currently, the dominant approach to achieve this goal is design space exploration (DESIGN SPACE Exploration, DSE). This process typically involves iterative modification, mapping and evaluation of the hardware architecture with the aid of a compiler. However, this type of iterative method of "compiler in loop" has the fundamental disadvantage that the exploration direction of the hardware architecture and the actual mapping result of the software on the architecture are disjointed from each other. The concrete steps are as follows: The optimization efficiency is low, namely, each time the hardware parameters are slightly adjusted, a compiler is required to be re-called to map the target software to a new architecture, performance, power consumption and area (PPA) evaluation is carried out, and huge and unnecessary exploration expenditure is generated. Optimization objective fracturing existing DSE flows consider "architecture modification" and "software mapping evaluation" as two separate phases. The mutation of the hardware architecture (such as increasing or decreasing functional units and changing interconnection) is based on the 'post' analysis of the mapping result of the previous round, rather than the 'pre' guidance performed in cooperation with the mapping process, so that the searching process is blind and difficult to globally optimize. The lack of a unified abstraction layer, existing compiler intermediate representation (INTERMEDIATE REPRESENTATION, IR) or hardware-oriented descriptions (e.g., LLVM IR, MLIR, architecture description graph ADG), is mainly used in a single field, either to describe only software logic and data flow (i.e., the logical trend of the data processed by the software), or to describe only static hardware structures. The lack of a unified intermediate representation that can simultaneously and explicitly express physical hardware resource characteristics and virtual mapping results of software thereon makes it difficult to formalize and efficiently solve the hardware-software co-optimization problem. Disclosure of Invention An object of the present invention is to construct a compiling method and device, which aims to solve at least part of the above technical problems. Another object of the present invention is to provide a compiling apparatus. Another object of the present invention is to provide an electronic device comprising a memory storing a computer program and a processor implementing the steps of the compiling method described above when the processor executes the computer program. It is a further object of the present invention to provide a readable medium having stored thereon a computer program which, when executed by a processor, implements the steps of the compiling method described above. In order to solve the technical problems in the background technology of the application, the application provides the following technical scheme: In a first aspect, the present invention provides a compiling method comprising: Mapping operator nodes of a predetermined target application to a virtual processing unit; generating a PE array according to a plurality of virtual processing units, wherein the PE array is used for representing the operator nodes executed by the virtual processing units, corresponding execution clock periods, hardware functional units supported by the virtual processing units and data dependency relations among the operator nodes; And generating the hardware description language code of the target application according to the PE array. In one embodiment of the present invention, generating the hardware description language code of the target application according to the PE array includes: Generating a first constraint condition according to the number of the hardware functional un