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CN-121996297-A - Instruction sending method, device, computer equipment and medium

CN121996297ACN 121996297 ACN121996297 ACN 121996297ACN-121996297-A

Abstract

The specification relates to the technical field of electronic circuits, in particular to an instruction sending method, an instruction sending device, computer equipment and a medium, wherein the method comprises the steps of adopting a mask circuit to carry out first comparison on a number of a target register to be sent and a number of a source register in a transmission queue to obtain a first comparison result; and determining whether a matching signal is generated according to the first comparison result, if so, performing second comparison on the number of the target register to be sent and the number of the source register to obtain a second comparison result, and if the second comparison result is consistent, sending the number of the target register to be sent to an execution unit for execution. The application reduces the comparison times, avoids redundant operation and controls the power consumption of the processor.

Inventors

  • FU MINGANG

Assignees

  • 成都群芯微电子科技有限公司

Dates

Publication Date
20260508
Application Date
20251219

Claims (13)

  1. 1. A method of transmitting instructions, the method comprising: The method comprises the steps of performing first comparison on a target register number to be sent and a source register number in a transmission queue by adopting a mask circuit to obtain a first comparison result; Determining whether to generate a matching signal according to the first comparison result; if yes, performing second comparison on the number of the target register to be sent and the number of the source register to obtain a second comparison result; and when the second comparison result is consistent, the number of the destination register to be sent is sent to an execution unit for execution.
  2. 2. The method of claim 1, wherein prior to first comparing the destination register number to be transmitted with the source register number in the transmit queue, the method comprises: judging whether the source register is in a ready state currently or not; If not, the number of the destination register to be sent is compared with the number of the source register in the transmitting queue for the first time.
  3. 3. The method of claim 1, wherein the performing a first comparison comprises: Bits of a preset position in the destination register number, and comparing the bit with the same preset position in the source register number.
  4. 4. The method of claim 3, wherein comparing bits of the predetermined location in the destination register number with bits of the same predetermined location in the source register number further comprises: Comparing the last N bits of all bits in the destination register number with the last N bits of all bits in the source register number, wherein N is a positive integer greater than 1.
  5. 5. The method of claim 1, wherein determining whether to generate a match signal based on the first comparison result comprises: Judging whether the first comparison signals are consistent; If yes, a matching signal is generated.
  6. 6. The method of claim 1, wherein the second comparing the destination register number to be sent with the source register number comprises: And respectively comparing other bits outside the preset position of the target register with other bits outside the preset position of the source register.
  7. 7. A masking circuit for use in the method of any one of claims 1 to 6, the circuit comprising a control circuit and a comparison circuit; The control circuit is used for performing first comparison on the number of the destination register to be sent and the number of the source register in the transmission queue to obtain a first comparison result; And the comparison circuit is used for performing second comparison on the number of the destination register to be sent and the number of the source register to obtain a second comparison result.
  8. 8. The circuit of claim 7, wherein the control circuit further comprises an exclusive OR gate and a first tri-state gate; the first tri-state gate is enabled by a source register in the transmitting queue, and obtains an output signal based on a bit of a preset position of a destination register; the output signal and the bit of the preset position of the source register are respectively used as the input end of the exclusive-or gate; The comparison circuit comprises a second tri-state gate, wherein the enabling end of the second tri-state gate is connected with the output end of the exclusive-or NOT gate, and the input of the second tri-state gate is other bits beyond the preset position of the target register.
  9. 9. The circuit of claim 8, wherein the masking circuit comprises a multi-level sub-masking circuit, each of the multi-level sub-masking circuits comprising an exclusive-or gate and a tri-state gate; The output of the tri-state gate in the upper-stage sub-mask circuit is the input of the tri-state gate and the exclusive-or gate in the lower-stage sub-mask circuit.
  10. 10. The circuit of claim 9, wherein the comparison circuit further comprises: And the judging module is connected with the output end of the second tri-state gate and the source register and is used for carrying out second comparison on the number of the destination register to be sent and the number of the source register to obtain a second comparison result.
  11. 11. An instruction transmitting apparatus, characterized in that the apparatus comprises: The first comparison unit is used for carrying out first comparison on the number of the target register to be transmitted and the number of the source register in the transmission queue by adopting the mask circuit to obtain a first comparison result; a generating unit, configured to determine whether to generate a matching signal according to the first comparison result; The second comparing unit is used for performing second comparison on the number of the destination register to be sent and the number of the source register if yes, so as to obtain a second comparison result; And the sending unit is used for sending the number of the destination register to be sent to the execution unit for execution when the second comparison result is consistent.
  12. 12. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method of any one of claims 1 to 6 when the computer program is executed.
  13. 13. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program which, when executed by a processor, implements the method of any one of claims 1 to 6.

Description

Instruction sending method, device, computer equipment and medium Technical Field The present disclosure relates to the field of electronic circuits, and in particular, to a method, an apparatus, a computer device, and a medium for sending instructions. Background Modern high performance CPUs commonly employ designs that combine Out-of-Order Execution (OoOE) with superscalar (Superscalar), which promote Instruction Level Parallelism (ILP) by dynamically scheduling instructions. An Issue Queue (Issue Queue) for buffering decoded instructions and dynamically scheduling ready instructions to the execution units; And the instruction transmitted to the execution Unit can be transmitted to the execution Unit for execution, wherein the destination register number (dst_tag) of the instruction is compared with all source register numbers (src_tag) of the instructions in the Issu Queue, the source registers with equal comparison results are marked as ready states, and the above process is the process of instruction wakeup (Wake) when all source registers of one instruction in the Issu Queue are marked as ready. However, under such an IssuQuue structure, one destination register will be compared with all source registers in IssuQuue, but in most cases only some source registers can be successfully matched, and the unmatched comparison will cause a large amount of invalid power consumption, furthermore, an superscalar processor will normally transmit multiple instructions to an execution unit every cycle, and send multiple destination registers to compare in IssuQuue, which will increase the invalid power consumption times, and in such a way, the full-association matching mode will cause a critical path delay and a sharp increase in clock tree power consumption, increasing manufacturing difficulty. Disclosure of Invention In order to solve the problems in the prior art, the specification provides an instruction sending method, an instruction sending device, computer equipment and a medium, wherein the method comprises the steps of adopting a mask circuit to carry out first comparison on a number of a target register to be sent and a number of a source register in a transmission queue to obtain a first comparison result; and determining whether a matching signal is generated according to the first comparison result, if so, performing second comparison on the number of the target register to be sent and the number of the source register to obtain a second comparison result, and if the second comparison result is consistent, sending the number of the target register to be sent to an execution unit for execution. According to one aspect of the embodiments of the present disclosure, before performing a first comparison between a destination register number to be sent and a source register number in a transmit queue, the method includes determining whether the source register is currently in a ready state, and if not, performing a first comparison between the destination register number to be sent and the source register number in the transmit queue. According to one aspect of the embodiments of the present disclosure, the performing the first comparison includes comparing bits of a preset location in the destination register number with bits of the same preset location in the source register number. According to one aspect of the embodiments of the present disclosure, comparing the bits of the preset position in the destination register number with the bits of the same preset position in the source register number further includes comparing the last N bits of all bits in the destination register number with the last N bits of all bits in the source register number, where N is a positive integer greater than 1. According to one aspect of the embodiments of the present disclosure, determining whether to generate the matching signal according to the first comparison result includes determining whether the first comparison signals are identical, and if so, generating the matching signal. According to one aspect of the embodiments of the present disclosure, the second comparison of the destination register number to be transmitted with the source register number includes comparing bits other than the destination register preset position with bits other than the source register preset position at the same position, respectively. The embodiment of the specification provides a mask circuit, which comprises a control circuit and a comparison circuit; The control circuit is used for carrying out first comparison on the number of the destination register to be sent and the number of the source register in the transmission queue to obtain a first comparison result, and the comparison circuit is used for carrying out second comparison on the number of the destination register to be sent and the number of the source register to obtain a second comparison result. According to one aspect of the embodiment of the specification, the control