CN-121996345-A - System-on-chip simulation method, device, electronic equipment and storage medium

Abstract

The embodiment of the disclosure provides a system-on-chip simulation method, a device, electronic equipment and a storage medium. The system-on-chip simulation method is realized based on a system simulator and comprises the steps of realizing coupling between a first subsystem and a second subsystem which are operated on a host based on an inter-core communication mechanism, wherein the first subsystem is a simulation model obtained based on simulation of the system simulator, the second subsystem is a simulation model operated as an independent process, and realizing coupling between the first subsystem and a third subsystem which are operated on the host based on function call, and the third subsystem is a simulation model in a source code or static library form. According to the system-on-chip simulation method provided by the embodiment of the disclosure, a general subsystem integration framework is established according to the characteristics of the subsystem, and when a new chip design is introduced, new components can be integrated into an existing system more easily, so that the workload of system-level integration is reduced, and the development efficiency is improved.

Inventors

• Wang Minfan
• WANG CONG
• YAN XIAOBO
• WANG JIAN
• ZHANG YONGSU
• ZHANG YU

Assignees

• 脸萌有限公司
• 北京有竹居网络技术有限公司

Dates

Publication Date

20260508

Application Date

20241106

Claims (15)

1. 1. A system-on-chip simulation method, based on a system simulator, comprising: Coupling between a first subsystem and a second subsystem running on a host is realized based on an inter-core communication mechanism, wherein the first subsystem is a simulation model obtained based on simulation of a system simulator, and the second subsystem is a simulation model running as an independent process; Coupling between the first subsystem and a third subsystem running on the host is achieved based on function calls, wherein the third subsystem is a simulation model in the form of source code or a static library.
2. 2. The system-on-chip simulation method of claim 1, wherein the first subsystem comprises at least one system simulation device comprising a preset system simulation device and a custom system simulation device.
3. 3. The system-on-chip simulation method of claim 1, further comprising: Coupling between a plurality of the first subsystems running on the host is achieved based on the inter-core communication mechanism.
4. 4. The system-on-chip emulation method of claim 3, wherein the inter-core based communication mechanism enables coupling between a plurality of the first subsystems running on the host, comprising: Coupling between a plurality of said first subsystems is achieved based on message queues and/or shared memory.
5. 5. The system-on-chip emulation method of claim 1, wherein the inter-core based communication mechanism enables coupling between a first subsystem and a second subsystem running on a host, comprising: The coupling between the first subsystem and the second subsystem is achieved based on a message queue and/or a shared memory.
6. 6. The system-on-chip simulation method of claim 1, wherein the third subsystem is a simulation model in source code form, the function call-based coupling between the first subsystem and the third subsystem running on the host comprises: compiling a simulation model of the third subsystem into a static library; And calling an interface function in the static library in the code of the system simulation equipment included in the first subsystem.
7. 7. The system-on-chip simulation method of claim 1, wherein the second subsystem and the third subsystem are simulated based on a simulator other than the system simulator.
8. 8. The system-on-chip simulation method of claim 1, wherein the second subsystem and the third subsystem are derived by multiplexing simulation models developed in a register transfer level design.
9. 9. The system-on-chip simulation method of claim 1, wherein the second subsystem comprises a simulation model of a processor, the simulation model of the processor running as a stand-alone process supporting an operating system for running on the processor.
10. 10. The system-on-chip simulation method of claim 1, wherein the second subsystem comprises a simulation model of a peripheral, the simulation model of the peripheral running as an independent process with independent resource management functionality.
11. 11. The system-on-chip simulation method of claim 1, wherein the second subsystem and the third subsystem are SystemC models.
12. 12. The system-on-chip simulation method of claim 1, wherein the system simulator is a QEMU simulator.
13. 13. A system-on-chip simulation apparatus, based on a system simulator, comprising: The first coupling module is configured to realize coupling between a first subsystem and a second subsystem which are operated on a host based on an inter-core communication mechanism, wherein the first subsystem is a simulation model obtained based on simulation of a system simulator, and the second subsystem is a simulation model operated as an independent process; and a second coupling module configured to enable coupling between the first subsystem and a third subsystem running on the host based on a function call, wherein the third subsystem is a simulation model in the form of source code or a static library.
14. 14. An electronic device, comprising: at least one processor; at least one memory including one or more computer program modules; Wherein the one or more computer program modules are stored in the at least one memory and configured to be executed by the at least one processor, the one or more computer program modules being for implementing the system-on-chip simulation method of any of claims 1-12.
15. 15. A non-transitory readable storage medium having stored thereon computer instructions, wherein the computer instructions, when executed by at least one processor, implement the system-on-chip simulation method of any of claims 1-12.

Description

System-on-chip simulation method, device, electronic equipment and storage medium Technical Field Embodiments of the present disclosure relate to a system-on-chip simulation method, apparatus, electronic device, and storage medium. Background A System on a Chip (SoC) is an integrated circuit that integrates all components required for the System onto the same Chip. These components, including, for example, a central processing unit (Central processing unit, CPU), memory, input/output ports, auxiliary memory, etc., are all packaged on a single silicon chip. The SoC design may include digital logic, analog circuitry, mixed signal processing, and Radio Frequency (RF) communication functions, depending on the particular application scenario. For next generation semiconductor development, more and more complex hardware and software integration is a significant challenge. In the conventional development mode, most of software development and verification work is usually performed after the hardware design is finalized, so that the urgent product development progress cannot be satisfied. Furthermore, hardware simulation platforms have limited resources and slow running speeds, especially when executing operating systems, which further exacerbates the development cycle pressure. In this context, the simulator is particularly important as an efficient tool. They can provide a system-wide level virtualized environment, greatly improving the efficiency of development and debugging efforts. By using the emulator, a software engineer may perform development work before the hardware design is completed, so that the software part may be immediately put into use when the physical chip is ready. This approach not only shortens product lead times, but also promotes overall supply chain performance improvement. Disclosure of Invention This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. The system simulator comprises a first subsystem and a second subsystem which are operated on a host based on an inter-core communication mechanism, wherein the first subsystem is a simulation model obtained based on simulation of the system simulator, the second subsystem is a simulation model operated as an independent process, and the coupling between the first subsystem and a third subsystem operated on the host is realized based on function call, wherein the third subsystem is a simulation model in a source code or static library form. At least one embodiment of the present disclosure provides a system-on-chip simulation apparatus, based on a system simulator, including a first coupling module configured to implement coupling between a first subsystem and a second subsystem running on a host based on an inter-core communication mechanism, where the first subsystem is a simulation model obtained based on simulation by the system simulator, and the second subsystem is a simulation model running as an independent process, and a second coupling module configured to implement coupling between the first subsystem and a third subsystem running on the host based on a function call, where the third subsystem is a simulation model in the form of a source code or a static library. At least one embodiment of the present disclosure provides an electronic device comprising at least one processor, at least one memory including one or more computer program modules, wherein the one or more computer program modules are stored in the at least one memory and configured to be executed by the at least one processor, the one or more computer program modules configured to implement the system-on-chip simulation method provided by the at least one embodiment. At least one embodiment of the present disclosure provides a non-transitory readable storage medium having stored thereon computer instructions, wherein the computer instructions, when executed by at least one processor, implement the system-on-chip simulation method provided in at least one embodiment described above. Drawings The above and other features, advantages, and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. The same or similar reference numbers will be used throughout the drawings to refer to the same or like elements. It should be understood that the figures are schematic and that elements and components are not necessarily drawn to scale. FIG. 1 is a flow chart of a system-on-chip simulation method provided in at least one embodiment of the present disclosure; FIG. 2 is a schematic diagram of a system-on-chip simulation method according to at least one embodiment of the present disclosu