CN-121996363-A - Interrupt control method, device and system based on RISC-V architecture

CN121996363ACN 121996363 ACN121996363 ACN 121996363ACN-121996363-A

Abstract

An interrupt control method, device and system based on RISC-V architecture. The interrupt control method comprises the steps of responding to a currently received interrupt signal, driving a global interrupt control register to shield global interrupt, obtaining interrupt information of the interrupt signal from an interrupt signal recording register, identifying whether the interrupt signal is a preset pseudo NMI interrupt or not based on the interrupt information, starting an NMI interrupt processing mechanism to respond to the pseudo NMI interrupt when the interrupt signal is the pseudo NMI interrupt, starting a common interrupt processing mechanism when the interrupt signal is the non-pseudo NMI interrupt, and driving the pseudo NMI interrupt control register to shield the newly-generated non-pseudo NMI interrupt and starting the NMI interrupt processing mechanism to respond to the newly-generated pseudo NMI interrupt. The interrupt control method realizes an NMI interrupt processing mechanism of a RISC-V architecture, and improves the response speed of the pseudo NMI interrupt corresponding to a single interrupt source.

Inventors

LU XU
Li Hangjing
DENG LIANG
XIE YONGJI
CHAI WEN
ZHANG YU
WANG JIAN

Assignees

北京有竹居网络技术有限公司

Dates

Publication Date: 20260508
Application Date: 20241105

Claims (12)

1. An interrupt control method based on RISC-V architecture, comprising: Responding to the currently received interrupt signal, and driving a global interrupt control register to shield global interrupt; Obtaining interrupt information of the interrupt signal from an interrupt signal recording register, and identifying whether the interrupt signal is a preset pseudo NMI interrupt or not based on the interrupt information; when the interrupt signal is identified as the pseudo NMI interrupt, starting an NMI interrupt processing mechanism to respond to the pseudo NMI interrupt; When the interrupt signal is identified as non-pseudo NMI interrupt, a common interrupt processing mechanism is started, a pseudo NMI interrupt control register is driven to shield the newly generated non-pseudo NMI interrupt, and the NMI interrupt processing mechanism is started to respond to the newly generated pseudo NMI interrupt.
2. The interrupt control method according to claim 1, wherein an interrupt type of a single interrupt source to be preferentially responded to is set as the pseudo NMI interrupt.
3. The interrupt control method according to claim 1 or 2, wherein when the interrupt signal is identified as the pseudo NMI interrupt, enabling an NMI interrupt handling mechanism to respond to the pseudo NMI interrupt, comprises: Executing a starting program of the NMI interrupt processing mechanism to process the pseudo NMI interrupt; and driving the global interrupt control register to be always in a control state for shielding the global interrupt in the process of processing the pseudo NMI interrupt.
4. The interrupt control method according to claim 1 or 2, wherein when the interrupt signal is identified as a non-pseudo NMI interrupt, enabling a normal interrupt handling mechanism and driving a pseudo NMI interrupt control register to mask a newly occurring non-pseudo NMI interrupt and enabling the NMI interrupt handling mechanism to respond to the newly occurring pseudo NMI interrupt, comprises: Executing a starting program of the common interrupt processing mechanism to process the non-pseudo NMI interrupt; in the process of processing the non-pseudo NMI interrupt, driving the pseudo NMI interrupt control register to control an NMI interrupt processing mechanism to be in an enabling state so as to respond to the subsequent newly-generated pseudo NMI interrupt and shield the subsequent newly-generated non-pseudo NMI interrupt; Driving the global interrupt control register to unmask the global interrupt; In response to the occurrence of the pseudo NMI interrupt, calling an interrupt processing function to execute the NMI interrupt processing mechanism; And in response to the execution end of the NMI interrupt processing mechanism, driving the global interrupt control register to mask the global interrupt and driving the pseudo NMI interrupt control register to reset.
5. The interrupt control method according to claim 1 or 2, wherein the global interrupt control register employs SSTATUS registers, the interrupt signal recording register employs SCAUSE registers, and the pseudo NMI interrupt control register employs SIE registers.
6. The interrupt control method according to claim 1 or 2, wherein the global interrupt control register has stored therein at least a control instruction for masking the global interrupt and a control instruction for unmasking the global interrupt, and The pseudo NMI interrupt control register at least stores a control instruction for controlling the NMI interrupt processing mechanism to be in an enabling state and shielding the non-pseudo NMI interrupt, and a control instruction for ending the NMI interrupt processing mechanism to be in the enabling state and shielding the non-pseudo NMI interrupt.
7. The interrupt control method of claim 2, wherein the interrupt type of the single interrupt source comprises at least one of a software interrupt, a clock interrupt, an external interrupt, or a PMU interrupt.
8. The interrupt control method of claim 7 wherein the dummy NMI interrupt control register has interrupt enable bits disposed therein that correspond to the number of dummy NMI interrupts, the interrupt enable bits including at least one of SSIE interrupt enable bits, STIE interrupt enable bits, SEIE interrupt enable bits, PMUOVF interrupt enable bits, The SSIE interrupt enable bit is used for controlling the enabling of the software interrupt; The STIE interrupt enable bit is used for controlling the enabling of the clock interrupt; the SEIE interrupt enable bit is used for controlling the enabling of the external interrupt; The PMUOVF interrupt enable bit is used to control the enabling of the PMU interrupt.
9. The interrupt control method according to claim 1 or 2, characterized by further comprising: Before executing the WFI instruction, identifying whether the non-pseudo NMI interrupt is shielded at the current moment according to the setting of the pseudo NMI interrupt control register; If yes, driving the global interrupt control register to shield the global interrupt, driving the pseudo NMI interrupt control register to control the non-NMI interrupt to be in an enabling state at the current moment, and then executing the WFI instruction; Otherwise, the WFI instruction is directly executed.
10. The interrupt control method according to claim 1 or 2, characterized by further comprising: and resetting the global interrupt control register, the interrupt signal recording register and the pseudo NMI control register after the pseudo NMI interrupt is ended.
11. An interrupt control device based on RISC-V architecture, comprising: A first processing unit configured to drive a global interrupt control register to mask a global interrupt in response to a currently received interrupt signal; A second processing unit configured to acquire interrupt information of the interrupt signal from an interrupt signal recording register, and identify whether the interrupt signal is a preset pseudo NMI interrupt based on the interrupt information; A first interrupt control unit configured to enable an NMI interrupt handling mechanism in response to the dummy NMI interrupt when the interrupt signal is identified as the dummy NMI interrupt; And the second interrupt control unit is configured to enable a common interrupt processing mechanism when the interrupt signal is identified as a non-pseudo NMI interrupt, drive a pseudo NMI interrupt control register to shield the newly-generated non-pseudo NMI interrupt and enable the NMI interrupt processing mechanism to respond to the newly-generated pseudo NMI interrupt.
12. An interrupt control system based on RISC-V architecture, comprising: A global interrupt control register configured to issue a control instruction to mask a global interrupt, or to issue a control instruction to unmask the global interrupt; An interrupt signal recording register configured to record and store an interrupt signal; A pseudo NMI interrupt control register configured to issue a control instruction that controls an NMI interrupt handling mechanism to be in an enabled state and masks a non-pseudo NMI interrupt, or issue a control instruction that ends the NMI interrupt handling mechanism to be in an enabled state and masks the non-pseudo NMI interrupt; a controller configured to drive the global interrupt control register, the interrupt signal recording register, the pseudo NMI interrupt control register and to perform the interrupt control method of any one of claims 1-10.

Description

Interrupt control method, device and system based on RISC-V architecture Technical Field The embodiment of the disclosure relates to an interrupt control method, device and system based on a RISC-V architecture. Background While the operating system of the computer explicitly masks the interrupt signal, the non-maskable interrupt (Non Maskable Interrupt, abbreviated as NMI interrupt) can still interrupt the execution of the operating system, informing the operating system to perform urgent tasks, such as handling serious system exceptions, faults, and the like. Disclosure of Invention This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. At least one embodiment of the present disclosure provides an interrupt control method based on a RISC-V architecture, including driving a global interrupt control register to mask a global interrupt in response to a currently received interrupt signal, acquiring interrupt information of the interrupt signal from an interrupt signal recording register, identifying whether the interrupt signal is a preset pseudo NMI interrupt based on the interrupt information, enabling an NMI interrupt processing mechanism to respond to the pseudo NMI interrupt when the interrupt signal is the pseudo NMI interrupt is identified, enabling a normal interrupt processing mechanism when the interrupt signal is identified as a non-pseudo NMI interrupt, and driving a pseudo NMI interrupt control register to mask a newly generated non-pseudo NMI interrupt and enabling the NMI interrupt processing mechanism to respond to the newly generated pseudo NMI interrupt. The at least one embodiment of the present disclosure also provides an interrupt control device based on a RISC-V architecture, which includes a first processing unit configured to drive a global interrupt control register to mask a global interrupt in response to a currently received interrupt signal, a second processing unit configured to acquire interrupt information of the interrupt signal from an interrupt signal recording register and identify whether the interrupt signal is a preset pseudo NMI interrupt based on the interrupt information, a first interrupt control unit configured to identify that the interrupt signal is the pseudo NMI interrupt, enable an NMI interrupt processing mechanism to respond to the pseudo NMI interrupt, and a second interrupt control unit configured to enable a normal interrupt processing mechanism and drive a pseudo NMI interrupt control register to mask a newly generated non-pseudo NMI interrupt and enable the NMI interrupt processing mechanism to respond to the newly generated pseudo NMI interrupt when the interrupt signal is identified as a non-pseudo NMI interrupt. The at least one embodiment of the present disclosure also provides an interrupt control system based on a RISC-V architecture, which includes a global interrupt control register configured to issue a control instruction to mask a global interrupt or issue a control instruction to release the masking of the global interrupt, an interrupt signal recording register configured to record and store an interrupt signal, a pseudo NMI interrupt control register configured to issue a control instruction to control an NMI interrupt processing mechanism to be in an enabled state and mask a non-pseudo NMI interrupt or issue a control instruction to end the NMI interrupt processing mechanism to be in an enabled state and mask a non-pseudo NMI interrupt, and a controller configured to drive the global interrupt control register, the interrupt signal recording register, and the pseudo NMI interrupt control register to execute the interrupt control method provided by the at least one embodiment of the present disclosure. Drawings The above and other features, advantages, and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. The same or similar reference numbers will be used throughout the drawings to refer to the same or like elements. It should be understood that the figures are schematic and that elements and components are not necessarily drawn to scale. Fig. 1 shows a flowchart of an interrupt control method provided by at least one embodiment of the present disclosure. Fig. 2 illustrates a flow chart of a process for handling a pseudo NMI interrupt that prevents infinite nesting of pseudo NMI interrupts provided by at least one embodiment of the present disclosure. Fig. 3 illustrates a flow chart of a process for handling non-pseudo NMI interrupts to prevent nesting of non-pseudo NMI interrupts provided by at least one embodiment of the present discl