CN-121996370-A - Dual-core processor task scheduling and processing method and device for multichannel vibration data acquisition system

CN121996370ACN 121996370 ACN121996370 ACN 121996370ACN-121996370-A

Abstract

The invention discloses a task scheduling and processing method and device of a dual-core processor for a multi-channel vibration data acquisition system, wherein the system comprises a Field Programmable Gate Array (FPGA) and a Loongson processor comprising a first processor core and a second processor core; the method comprises the steps of performing data acquisition through FPGA response configuration, asynchronously transmitting acquired data to a target data block of a shared memory area through a DMA transmission channel, monitoring the transmission state of the shared memory area through a second processor core, preprocessing the original acquired data written into the target data block, acquiring the preprocessed data through a first processor core, executing a core data processing algorithm, realizing the whole-flow optimization of vibration data from acquisition and transmission to processing, and guaranteeing the instantaneity and reliability of core processing tasks.

Inventors

WANG JI
XU JIAN
SHI WEI
LAO LIHUI
WANG GUODONG
YU DONG
YU XIANG

Assignees

浙江至控科技有限公司

Dates

Publication Date: 20260508
Application Date: 20251205

Claims (10)

1. The task scheduling and processing method for the dual-core processor of the multichannel vibration data acquisition system is characterized in that the system comprises a Field Programmable Gate Array (FPGA) and a Loongson processor comprising a first processor core and a second processor core, and the method comprises the following steps: Starting a first processor to check the FPGA to perform data acquisition parameter configuration, and initializing at least one Direct Memory Access (DMA) transmission channel pointing to a shared memory area; Performing data acquisition through FPGA response configuration, and asynchronously transmitting acquired data to a target data block of the shared memory area through the DMA transmission channel; Monitoring the transmission state of the shared memory area through a second processor core, and preprocessing the original acquired data written into the target data block; Acquiring the preprocessed data through a first processor core and executing a core data processing algorithm; and accessing and updating state information in the shared memory area through atomic operation between the first processor core and the second processor core to realize task coordination, wherein the state information is at least used for identifying the occupation or ready state of each data block in the shared memory area.
2. The dual-core processor task scheduling and processing method for a multi-channel vibratory data acquisition system of claim 1, wherein the initiating the first processor checks the FPGA for data acquisition parameter configuration prior to system initialization: Loading and initializing a hardware driver of the FPGA, and establishing a control and communication link between the Loongson processor and the FPGA; configuring the shared memory area, dividing the shared memory area into at least two physically continuous data blocks, and initializing state variables for identifying the states of the data blocks; Configuring a plurality of transmission descriptors to a DMA controller of the FPGA through a driver program, wherein each transmission descriptor is respectively associated with a physical address and a transmission length of a data block in the shared memory area; Configuring acquisition parameters to the FPGA through register reading and writing, wherein the parameters at least comprise the number of sampling channels, sampling rate, sampling points, a digital filter mode, measuring range size and a coupling mode; And setting the core processing task running on the first processor core into a waiting state, and waking up the monitoring and preprocessing task running on the second processor core through inter-processor interrupt.
3. The dual processor task scheduling and processing method for a multi-channel vibratory data acquisition system of claim 1, wherein the shared memory area is configured as a ring buffer comprising at least two logical data blocks, and the DMA transfer channel is configured to write data to each logical data block in a sequential loop such that the second processor core can process the written data blocks to enable pipelining of data acquisition, transfer, and preprocessing.
4. The dual processor task scheduling and processing method for a multi-channel vibratory data acquisition system of claim 3, wherein the ring buffer is associated with a state structure comprising the following variables accessed by atomic operations: a producer index indicating a logical data block to which the DMA controller should currently write; A consumer index indicating logical data blocks that the second processor core should currently read and pre-process; a ready flag or index to indicate that preprocessing has been completed, a logical data block available for the first processor core to acquire data; a transfer complete flag for atomically identifying that a DMA write operation for a logical data block has been completed.
5. The dual-core processor task scheduling and processing method for a multi-channel vibratory data acquisition system of claim 1, wherein the performing data acquisition by FPGA response configuration and asynchronously transmitting the acquired data to the target data block of the shared memory area by the DMA transfer channel comprises: The FPGA controls the analog-to-digital converter ADC to collect frame data according to the configuration parameters, and the staggered sampling data of the multiple channels are cached in an internal first-in first-out FIFO memory; When the data amount cached in the FIFO memory reaches a preset threshold value, triggering a DMA controller of the FPGA to directly write data into a corresponding target data block in the shared memory area through a high-speed bus according to the current effective DMA descriptor; When one-time DMA transmission is completed, the DMA controller of the FPGA sends out a transmission completion interrupt to the Loongson processor; An interrupt service routine is executed by the Loongson processor in response to the interrupt and at least the operations of atomically setting the transfer complete flag, sending an inter-processor interrupt to the second processor core, and switching the currently active descriptor of the DMA controller to point to the next logical data block.
6. The dual processor task scheduling and processing method for a multi-channel vibratory data acquisition system of claim 4, wherein monitoring, by the second processor core, a transmission state of the shared memory area and preprocessing raw acquisition data written into the target data block comprises: detecting a new data block write completion event by polling the transfer completion flag or responding to an inter-processor interrupt; Determining the target data block according to the producer index, and sequentially executing operations of data validity verification, engineering unit conversion, preliminary digital filtering and data format rearrangement on the original data in the target data block; Writing the preprocessed data into an independent processed data buffer; atomically updating the ready flag or index to indicate that the data corresponding to the target data block has been preprocessed and optionally sending an inter-processor interrupt to the first processor core; the consumer index is atomically updated to release the target data block.
7. The dual-core processor task scheduling and processing method for a multi-channel vibratory data acquisition system of claim 1, wherein the acquiring of the preprocessed data by the first processor core and executing the core data processing algorithm comprises: When the high-priority real-time task on the first processor core runs, the high-priority real-time task is activated in a waiting state, a corresponding data block ready in a processed data buffer area is determined by accessing a producer index in the shared memory area, and preprocessed data in the data block is acquired; Performing fast Fourier transform operation on the data arranged according to the channels in the data block, respectively aiming at each channel, generating vibration frequency spectrums of the channels, and extracting preset power frequency characteristic components and amplitude and phase information thereof from the vibration frequency spectrums; The power frequency characteristic component, the amplitude and the phase information of the power frequency characteristic component are used as processing results and are sent to an upper computer or stored in a local database through an Ethernet; After the result output step is completed, the high-priority real-time task enters a blocking waiting state again until a next processing notification triggered by the second processor core is received, so that a periodic core processing loop is formed.
8. The dual-core processor task scheduling and processing method for a multi-channel vibratory data acquisition system of claim 1, wherein the first processor core and the second processor core are cooperatively task-implemented by atomic operations: triggering an interrupt service routine to atomically update a transfer completion flag and notifying the second processor core when a DMA transfer is completed; After the second processor core preprocessing is completed, an atom updates the ready flag or index and notifies the first processor core; after the core data of the first processor core is processed, waiting for a next round of processing notification, so as to form pipeline operation of acquisition, transmission, preprocessing and core data processing.
9. The dual processor task scheduling and processing method for a multi-channel vibratory data acquisition system of claim 1, further comprising an exception co-processing step of: Reporting to the first processor core through an error status identification in the shared memory area when the second processor core detects that data is invalid or exceeds a quantity threshold in a preprocessing process; Checking the error status identification before the first processor core executes a core data processing algorithm and performing operations including data dropping, error reporting or system reconfiguration according to a predefined policy.
10. A dual-core processor task scheduling and processing apparatus for implementing the method of any one of claims 1 to 6, comprising: the Loongson processor comprises a first processor core and a second processor core; the Field Programmable Gate Array (FPGA) is connected with the Loongson processor; the shared memory area is arranged in the system memory; The first processor core is configured to perform data acquisition parameter configuration on the FPGA, initialize at least one Direct Memory Access (DMA) transmission channel pointing to the shared memory area, acquire preprocessed data from the shared memory area and execute a core data processing algorithm; the FPGA is configured to respond to the configuration for data acquisition and asynchronously transmit acquired data to a target data block of the shared memory area through the DMA transmission channel; The second processor core is configured to monitor a transmission state of the shared memory area and pre-process the original acquired data written into the target data block; The shared memory area also stores state information, the state information can be accessed and updated by the first processor core and the second processor core through atomic operation so as to realize task coordination between the first processor core and the second processor core, and the state information is at least used for identifying the occupation state or the ready state of each data block in the shared memory area.

Description

Dual-core processor task scheduling and processing method and device for multichannel vibration data acquisition system Technical Field The invention relates to the technical field of industrial measurement and control and signal processing, in particular to a task scheduling and processing method and device for a dual-core processor of a multichannel vibration data acquisition system. Background In the fields of high-end equipment manufacturing, aerospace, rail transit and the like, on-line vibration monitoring of key equipment such as rotary machinery and the like is a core means of preventive maintenance. With the improvement of equipment precision and complexity, higher requirements are placed on a vibration data acquisition system, such as higher sampling rate (up to hundreds of KHz), more synchronous acquisition channels, lower transmission delay and stronger real-time processing capability. After having a powerful hardware platform (such as Loongson 2K1500+FPGA), how to efficiently and reasonably utilize multi-core CPU resources becomes a new challenge. Simple Symmetric Multiprocessing (SMP) modes may not meet the strict deterministic requirements for task execution timing in vibration signal processing due to inter-core communication (IPC) overhead and resource contention. If the task is not allocated properly, the data flow may be unsmooth, the processing delay may be increased, and the performance advantage of the hardware platform may not be exerted. Therefore, a new method capable of optimizing multi-core resource scheduling and guaranteeing data processing instantaneity and certainty is needed. Disclosure of Invention The invention aims to provide a task scheduling and processing method and device for a dual-core processor of a multichannel vibration data acquisition system, which are integrated with a dual-core processor platform of high-speed data acquisition hardware (FPGA+DMA), and realize the full-flow optimization of vibration data from acquisition and transmission to processing by an asymmetric task scheduling and data processing method, thereby ensuring the real-time performance and reliability of core processing tasks. The invention provides a task scheduling and processing method of a dual-core processor for a multichannel vibration data acquisition system, wherein the system comprises a Field Programmable Gate Array (FPGA) and a Loongson processor comprising a first processor core and a second processor core, and the method comprises the following steps: Starting a first processor to check the FPGA to perform data acquisition parameter configuration, and initializing at least one Direct Memory Access (DMA) transmission channel pointing to a shared memory area; Performing data acquisition through FPGA response configuration, and asynchronously transmitting acquired data to a target data block of the shared memory area through the DMA transmission channel; Monitoring the transmission state of the shared memory area through a second processor core, and preprocessing the original acquired data written into the target data block; Acquiring the preprocessed data through a first processor core and executing a core data processing algorithm; and accessing and updating state information in the shared memory area through atomic operation between the first processor core and the second processor core to realize task coordination, wherein the state information is at least used for identifying the occupation or ready state of each data block in the shared memory area. Preferably, before the first processor is started to check the FPGA to perform data acquisition parameter configuration, the method further includes system initialization: Loading and initializing a hardware driver of the FPGA, and establishing a control and communication link between the Loongson processor and the FPGA; configuring the shared memory area, dividing the shared memory area into at least two physically continuous data blocks, and initializing state variables for identifying the states of the data blocks; Configuring a plurality of transmission descriptors to a DMA controller of the FPGA through a driver program, wherein each transmission descriptor is respectively associated with a physical address and a transmission length of a data block in the shared memory area; The method comprises the steps of configuring acquisition parameters to the FPGA through register reading and writing, wherein the parameters at least comprise sampling channel number, sampling rate, sampling point, number filter mode, measuring range size and coupling mode, setting a core processing task running on a first processor core into a waiting state, and waking up a monitoring and preprocessing task running on a second processor core through inter-processor interrupt. Preferably, the shared memory area is configured as a ring buffer, and includes at least two logic data blocks, and the DMA transfer channel is configured to write data to each logic