CN-121996470-A - Memory device and method for programming

Abstract

A memory device and method for programming are provided. The memory device may include a plurality of nonvolatile memories and a memory controller electrically connected to the plurality of nonvolatile memories through a plurality of channels and a plurality of paths. Multiple vias may be included in a via group. The memory controller may be configured to pre-program the input data into the plurality of non-volatile memories through a plurality of lanes, and after the pre-programming is completed, re-program the input data into the plurality of non-volatile memories through different ones of the lane groups during a period of time that does not overlap each other.

Inventors

• Jin Zhuanglv
• Pu Zhenyong
• Zhao Zhenzai
• JIN RENSHOU

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20251024

Priority Date

20241106

Claims (20)

1. 1. A storage device, comprising: A plurality of nonvolatile memories, and A memory controller electrically connected to the plurality of nonvolatile memories through a plurality of channels and a plurality of vias, wherein the plurality of vias are included in a via group, Wherein the storage controller is configured to: Pre-programming input data into the plurality of non-volatile memories through the plurality of passes, and After the pre-programming is completed, the input data is re-programmed into the plurality of non-volatile memories through different ones of the sets of paths during periods of time that do not overlap each other.
2. 2. The storage device of claim 1, further comprising a buffer memory configured to buffer the input data, Wherein each of the plurality of non-volatile memories is electrically connected to one of the plurality of channels through a respective one of the plurality of channels.
3. 3. The memory device of claim 1, wherein the memory controller is configured to reprogram the input data through a first one of the sets of lanes during one of the time periods.
4. 4. The storage device of claim 3, wherein the storage controller is configured to backup the input data of the first one of the lane groups in response to detecting a sudden power-off SPO event during the one of the time periods.
5. 5. The memory device of claim 1, wherein the memory controller is configured to set a number of vias included in each of the via groups.
6. 6. The memory device of claim 1, wherein the number of lane groups is two.
7. 7. The memory device of claim 1, wherein the memory controller is configured to pre-program additional input data into at least one of the plurality of non-volatile memories through one of the lane groups after the reprogramming of the input data through the one of the lane groups is completed.
8. 8. The storage device of claim 7, wherein the storage controller is configured to initiate the pre-programming of the additional input data by the one of the lane groups and the re-programming of the input data by another one of the lane groups simultaneously during one of the time periods.
9. 9. The storage device of claim 1, wherein the storage controller is configured to: dequeuing the command from the queue; Performing the pre-programming in response to the command indicating a pre-programming operation, and In response to the command not indicating a pre-program operation, a number of passes of the plurality of passes in which the re-programming is being performed is determined.
10. 10. The storage device of claim 9, wherein the storage controller is configured to: enqueuing the command in a pending queue in response to the number of lanes being greater than or equal to a predetermined threshold value, and The reprogramming is performed in response to the number of lanes being less than the predetermined threshold value.
11. 11. The memory device of claim 1, wherein a reprogramming verification voltage configured for the reprogramming is higher than a preprogrammed verification voltage configured for the preprogramming.
12. 12. A method of operating a storage device, the method comprising: Pre-programming input data into a plurality of non-volatile memories through a plurality of channels and a plurality of lanes, wherein the plurality of lanes are included in a lane group, and After the pre-programming is completed, the input data is re-programmed into the plurality of non-volatile memories through different ones of the sets of paths during periods of time that do not overlap each other.
13. 13. The method of claim 12, wherein the reprogramming is performed during one of the time periods by a first one of the sets of paths to reprogram the input data.
14. 14. The method of claim 13, further comprising: Detecting a sudden power off SPO event for the storage device, and In response to detecting the SPO event during the one of the time periods, the input data of the first one of the lane groups is backed up.
15. 15. The method of claim 12, further comprising setting a number of vias included in each of the via groups.
16. 16. The method of claim 12, further comprising pre-programming additional input data into at least one of the plurality of non-volatile memories through one of the lane groups after the reprogramming of the input data through the one of the lane groups is completed.
17. 17. The method of claim 12, further comprising: dequeuing the command from the queue; Performing the pre-programming in response to the command indicating a pre-programming operation, and In response to the command not indicating a pre-program operation, a number of passes of the plurality of passes in which the re-programming is being performed is determined.
18. 18. The method of claim 17, further comprising: enqueuing the command in a pending queue in response to the number of lanes being greater than or equal to a predetermined threshold value, and The reprogramming is performed in response to the number of lanes being less than the predetermined threshold value.
19. 19. A storage device, comprising: A plurality of nonvolatile memories, and A memory controller electrically connected to the plurality of nonvolatile memories through a plurality of channels and a plurality of paths, Wherein the storage controller is configured to: Pre-programming input data into the plurality of non-volatile memories through the plurality of passes, and During a period of time, reprogramming the input data into at least one of the plurality of non-volatile memories through a lane of the plurality of lanes, the number of lanes of the plurality of lanes being less than a predetermined threshold value.
20. 20. The storage device of claim 19, wherein the storage controller is configured to set the predetermined threshold value, and Wherein the predetermined threshold value is less than or equal to a total number of the plurality of lanes.

Description

Memory device and method for programming Cross Reference to Related Applications The present application claims priority from korean patent application No.10-2024-0156184 filed on 6 th 11 of 2024 to korean intellectual property office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field Example embodiments relate to a memory device and method for programming. Background The storage device may store data under control of a host device such as a computer, smart phone, or tablet. Most storage devices are powered by an external power source. However, the storage device is vulnerable to damage, including data loss, due to a failure of an external power source or a power failure such as a sudden power-off (SPO). To address the above power-related issues, auxiliary power devices may be included within the storage device to support data backup (or dump). However, the power source used for data backup may depend on the capacity of the auxiliary power device. Therefore, it would be beneficial to reduce the dependency on the capacity of auxiliary power devices and to improve data reliability by reducing the amount of data backed up during a power outage situation. Disclosure of Invention Example embodiments provide a memory device and a method for programming that can reduce the amount of data backup during a Sudden Power Off (SPO) event. According to some example embodiments, a memory device may include a plurality of non-volatile memories and a memory controller electrically connected to the plurality of non-volatile memories through a plurality of channels (channels) and a plurality of ways. Multiple vias may be included in a via group. The memory controller may be configured to pre-program the input data into the plurality of non-volatile memories through a plurality of lanes, and after the pre-programming is completed, re-program the input data into the plurality of non-volatile memories through different ones of the lane groups during a period of time that does not overlap each other. According to some example embodiments, a method of operating a memory device may include pre-programming input data into a plurality of non-volatile memories through a plurality of channels and a plurality of lanes, wherein the plurality of lanes are included in a lane group, and after the pre-programming is completed, re-programming the input data into the plurality of non-volatile memories through different lane groups of the lane group during a period of time that does not overlap each other. According to some example embodiments, a memory device may include a plurality of non-volatile memories and a memory controller electrically connected to the plurality of non-volatile memories through a plurality of channels and a plurality of paths. The memory controller may be configured to pre-program the input data into the plurality of non-volatile memories through the plurality of lanes during a period of time and to re-program the input data into at least one of the plurality of non-volatile memories through a lane of the plurality of lanes, the number of lanes of the plurality of lanes being less than a predetermined threshold value. Drawings FIG. 1 is a block diagram of a storage device according to an example embodiment. Fig. 2 is a block diagram illustrating an example of a memory controller of fig. 1 according to an example embodiment. Fig. 3 is a block diagram illustrating an example of the nonvolatile memory of fig. 1 according to an example embodiment. Fig. 4 is a circuit diagram illustrating an example of a memory block within the memory cell array of fig. 1 according to an example embodiment. Fig. 5 is a diagram illustrating data states based on a pre-program operation and a re-program operation according to an example embodiment. Fig. 6 and 7 are timing diagrams illustrating backup operations during a Sudden Power Off (SPO) event according to example embodiments. Fig. 8 and 9 are timing diagrams illustrating scheduling of a reprogramming method according to an example embodiment. Fig. 10 is a flowchart illustrating a method of operating a storage device according to an example embodiment. FIG. 11 is a flowchart illustrating a backup operation of a storage device according to an example embodiment. Fig. 12 is a flowchart illustrating a program scheduling method of a memory device according to an example embodiment. Fig. 13 is a block diagram of a storage device according to an example embodiment. Detailed Description Hereinafter, example embodiments will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of a storage device according to an example embodiment. Referring to fig. 1, a memory device 100 according to an example embodiment may include a memory controller 110, a plurality of nonvolatile memories 120, and a buffer memory 130. The memory controller 110 may be configured to control the plurality of nonvolatile memories 120 and the buffer memory