Search

CN-121996483-A - IST module, chip self-testing method, main board and computer equipment

CN121996483ACN 121996483 ACN121996483 ACN 121996483ACN-121996483-A

Abstract

The embodiment of the application provides an IST module, a chip self-testing method, a main board and computer equipment, wherein the IST module comprises an IST state machine, a reset control circuit and a reset control circuit, wherein the IST state machine is used for generating a global reset signal in an initialization stage of a test program, converting a test instruction into a JTAG signal for driving a TAP in an execution process of the test program, the reset control circuit is used for responding to an enabling state of a program continuing signal in the initialization stage of the test program, generating a local reset selection signal based on the global reset signal of the IST state machine and outputting the local reset selection signal to the TAP so as to drive the TAP to reset a routing network and keep the configuration of TDR, so that the IST state machine drives the TAP to execute chip testing based on the reserved configuration of the TDR in the execution process of the test program, and the routing network is used for forming an access path of a target TDR so as to test an on-chip module to be tested corresponding to the target TDR through the configuration of the target TDR. The embodiment of the application can improve the test scale of the IST mechanism of the chip and reduce the limitation of the IST mechanism.

Inventors

  • ZHANG SIZHE
  • ZHANG GUO
  • WANG PEIYU

Assignees

  • 海光云芯集成电路设计(上海)有限公司

Dates

Publication Date
20260508
Application Date
20251215

Claims (15)

  1. 1. An IST module for chip self-testing, comprising: The IST state machine is used for generating a global reset signal in the initialization stage of the test program, and converting a test instruction in the test program into a JTAG signal for driving the TAP in the execution process of the test program so as to execute chip test; The system comprises a reset control circuit, a test program, a local reset selection signal and a test program, wherein the reset control circuit is used for responding to the enabling state of a program continuing signal in the initialization stage of the test program, generating a local reset selection signal based on a global reset signal of an IST state machine and outputting the local reset selection signal to a TAP; The routing network is used for forming an access path of a target TDR to be accessed by the test program so as to test an on-chip module to be tested corresponding to the target TDR through configuration of the target TDR.
  2. 2. The IST module of claim 1, wherein the local reset select signal is a time series of TMS signals for driving the TAP into a TLR state such that the TAP generates a TLR signal in the TLR state, wherein the TLR signal acts on a reset port of the routing network to reset the routing network.
  3. 3. The IST module of claim 2, wherein the reset control circuit is further configured to output a global reset signal of the IST state machine to drive the TAP to perform a global reset if the program continuation signal is not enabled during an initialization phase of the test program; The global reset signal of the IST state machine is a TRST signal of the IST state machine and is used for driving the TAP to enter a TRST state, so that the TAP generates the TRST signal in the TRST state, the TRST signal acts on a reset port of the routing network and a reset port of a register set to carry out global reset, and the register set at least comprises a plurality of TDRs.
  4. 4. The IST module of claim 3, wherein the timing sequence of TMS signals is a high level TMS signal for at least a set number of clock cycles, the IST state machine is further configured to synchronously output TMS signals during an initialization phase of the test program; the reset control circuit comprises a first OR gate, a TCK counter, an inverter and a second OR gate; the first OR gate is used for responding to the enabling state of the program continuing signal in the initialization stage of the test program, shielding the TRST signal of the IST state machine from acting on the TAP so that the TRST signal of the IST state machine acts on the TCK counter, and outputting the TRST signal of the IST state machine to the TAP if the program continuing signal is not enabled; The TCK counter is used for starting counting based on a TRST signal of the IST state machine, counting the clock cycles corresponding to the TCK signal, and keeping outputting a low-level counting completion signal during the counting period until the counted clock cycles at least reach the set clock cycles; The inverter is used for performing inversion processing on a low-level counting completion signal output by the TCK counter in the counting period so as to maintain outputting a high-level signal in the counting period; the second OR gate is used for performing phase OR processing on the TMS signal of the IST state machine and the high-level signal which is maintained to be output by the inverter in the counting period so as to form the high-level TMS signal which lasts for at least a set clock cycle number and output the high-level TMS signal to the TAP.
  5. 5. The IST module of claim 4, wherein the IST state machine is further configured to execute a subsequent test instruction based on the fed-back high-level count completion signal to enter an execution process of the test program when the TCK counter finishes counting, wherein the high-level count completion signal is fed back to the IST state machine to indicate that the TAP finishes the local reset in the TLR state, so that the IST state machine executes the subsequent test instruction.
  6. 6. The IST module of any of claims 1-5, wherein an enabled state or an disabled state of the program continuation signal is based on a test plan indication; when the TDR configuration is required to be completed together by a plurality of test programs executed in segments, the test plan defines a connection relationship of the TDR configuration between the test programs, so as to indicate a program connection signal generating an enabling state, so that the TDR configuration is connected between the test programs.
  7. 7. The IST module of any of claims 1-5, further comprising a memory reader for reading test instructions in a test program from an on-chip memory of the chip and passing to an IST state machine.
  8. 8. A chip, comprising at least: The IST module as claimed in any of claims 1-7, wherein the IST module is configured to generate and output a local reset select signal to the TAP in response to an enable state of a program continuation signal at least during an initialization phase of the test program to drive the TAP reset routing network and preserve a configuration of the TDR, and to convert test instructions in the test program into JTAG signals driving the TAP to drive the TAP to perform a chip test based on the preserved TDR configuration during execution of the test program.
  9. 9. The chip of claim 8, further comprising: the TAP is used for resetting the routing network and reserving the configuration of the TDR if a local reset selection signal of the IST module is received in the initialization stage of the test program, and controlling the routing network and the register group to perform corresponding test operation based on the received JTAG signal of the IST module in the execution process of the test program; the routing network comprises a plurality of SIBs and a routing network, wherein the SIBs are used for establishing an access path of a target TDR to be accessed by the test program, the routing network is reset under the control of the TAP in an initialization stage of the test program, and the target SIBs in the routing network are configured to be in an open state under the control of the TAP in the execution process of the test program so as to form the access path of the access target TDR; The register set comprises a plurality of TDRs and is used for storing configuration data of the on-chip module to be tested corresponding to the TDRs, wherein in the initialization stage of the test program, if the TAP receives a local reset selection signal of the IST module, the configuration of the TDRs in the register set is reserved.
  10. 10. The chip of claim 9, wherein the TAP has a TLR state and a TRST state, the TLR state driven by a local reset select signal of the IST module and the TRST state driven by a global reset signal of the IST module, wherein during an initialization phase of the test program, if a program continuation signal is not enabled, the IST module outputs a global reset signal to the TAP; The TAP generates a TLR signal in a TLR state, and the TLR signal acts on a reset port of the routing network to reset the routing network; the TAP generates a TRST signal in a TRST state, and the TRST signal acts on a reset port of the routing network and a reset port of the register set to perform global reset; the chip further includes: The device comprises a TAP, an AND gate, a register group, a register, a data processing unit and a data processing unit, wherein the TAP is used for outputting TLR signals, TRST signals and a register group, the AND gate is positioned between the distribution paths of the TLR signals and the TRST signals of the TAP and the reset port of the routing network, and is used for distributing the TLR signals to the reset port of the routing network when the TAP outputs the TLR signals and distributing the TRST signals to the reset port of the routing network when the TAP outputs the TRST signals; and/or the number of the groups of groups, An on-chip memory for storing a test program for reading by the IST module; and/or the number of the groups of groups, And the on-chip module to be tested corresponds to the TDR and configures the configuration data required by the test through the corresponding TDR.
  11. 11. The chip of claim 9, wherein the TLR signal also acts on a reset port of a partial TDR in the register, the reset port of the partial TDR receiving the TLR signal generated by the TAP in the TLR state for resetting, wherein the partial TDR belongs to a TDR in the register set that stores confidential data, and wherein other TDRs in the register set other than the partial TDR remain configured in the TLR state of the TAP.
  12. 12. A method of chip self-testing, applied to the IST module of any of claims 1-7, comprising: Generating an initial global reset signal in an initialization stage of a test program, and acquiring a program continuing signal of an enabling state; Generating a local reset selection signal based on an enabling state of the program continuing signal and an initial global reset signal, wherein the local reset selection signal is used for driving the TAP reset routing network and keeping the configuration of the TDR; during execution of the test program, test instructions in the test program are converted into JTAG signals driving the TAP to drive the TAP to perform chip testing based on the reserved TDR configuration.
  13. 13. The method of claim 12, wherein the enabled state or the disabled state of the program continuation signal is based on a test plan indication; when the TDR configuration is required to be completed together by a plurality of test programs executed in segments, the test plan defines a connection relationship of the TDR configuration between the test programs, so as to indicate a program connection signal generating an enabling state, so that the TDR configuration is connected between the test programs.
  14. 14. A motherboard comprising a chip as claimed in any one of claims 8 to 11.
  15. 15. A computer device comprising a chip as claimed in any one of claims 8 to 11 or a motherboard as claimed in claim 14.

Description

IST module, chip self-testing method, main board and computer equipment Technical Field The embodiment of the application relates to the technical field of computers, in particular to an IST module, a chip self-testing method, a main board and computer equipment. Background In the manufacturing process of integrated circuits (such as very large scale integrated circuits), chips often have physical defects due to photolithography bias, metal interconnection defects, contact Kong Kailu, early failure of devices, etc., and in order to improve the yield and reliability of chips, test mechanisms based on JTAG (Joint Test Action Group, joint test working group) protocol are required to be introduced into the chips during the manufacturing process to identify the physical defects formed in the chips during the manufacturing process. Chip testing based on the JTAG protocol is typically accomplished on an ATE (Automatic Test Equipment, automated test equipment) bench or dedicated test board. However, when the chip is abnormally operated on the finally installed system board (i.e., motherboard), since the system board is not generally provided with a JTAG interface, JTAG signals cannot be applied to the TAP (TEST ACCESS Port ) through the system board, and at this time, the chip often needs to be detached from the system board and re-connected to an ATE machine or a dedicated test board in order to complete chip testing and abnormality analysis. The TAP is a standardized test access port based on JTAG protocol and is used for receiving JTAG signals so as to control a scanning chain in the chip to execute a test. The above-mentioned process is complex and has high risk, so that an IST (IN SYSTEM TEST, system self test) mechanism is introduced into the chip architecture, so that the chip can drive the TAP to perform chip test through an on-chip communication mode. At present, the test scale of the IST mechanism of the chip is limited, so how to provide a technical solution to improve the test scale of the IST mechanism of the chip and reduce the limitation of the IST mechanism becomes a technical problem to be solved by those skilled in the art. Disclosure of Invention In view of this, the embodiments of the present application provide an IST module, a chip self-testing method, a motherboard, and a computer device, so as to improve the testing scale of an IST mechanism of the chip and reduce the limitation of the IST mechanism. In order to achieve the above purpose, the embodiment of the present application provides the following technical solutions. In a first aspect, an embodiment of the present application provides an IST module for chip self-testing, including: The IST state machine is used for generating a global reset signal in the initialization stage of the test program, and converting a test instruction in the test program into a JTAG signal for driving the TAP in the execution process of the test program so as to execute chip test; The system comprises a reset control circuit, a test program, a local reset selection signal and a test program, wherein the reset control circuit is used for responding to the enabling state of a program continuing signal in the initialization stage of the test program, generating a local reset selection signal based on a global reset signal of an IST state machine and outputting the local reset selection signal to a TAP; The routing network is used for forming an access path of a target TDR to be accessed by the test program so as to test an on-chip module to be tested corresponding to the target TDR through configuration of the target TDR. In a second aspect, an embodiment of the present application provides a chip, including at least: The IST module of the first aspect is at least used for responding to the enabling state of the program continuing signal in the initialization stage of the test program, generating a local reset selection signal and outputting the local reset selection signal to the TAP so as to drive the TAP to reset the routing network and keep the configuration of the TDR, and converting the test instruction in the test program into the JTAG signal for driving the TAP in the execution process of the test program so as to drive the TAP to execute the chip test based on the kept TDR configuration. In a third aspect, an embodiment of the present application provides a chip self-testing method, applied to the IST module in the first aspect, including: Generating an initial global reset signal in an initialization stage of a test program, and acquiring a program continuing signal of an enabling state; Generating a local reset selection signal based on an enabling state of the program continuing signal and an initial global reset signal, wherein the local reset selection signal is used for driving the TAP reset routing network and keeping the configuration of the TDR; during execution of the test program, test instructions in the test program are converted into JTAG