CN-121996485-A - Processor test method, apparatus, computer device, readable storage medium, and program product

Abstract

The present application relates to a processor testing method, apparatus, computer device, computer readable storage medium and computer program product. The method comprises the steps of obtaining test case data of a target processor, wherein the test case data comprise test identifications, test instruction types, priorities, test instruction descriptions and generation prompt words, processing test constraint data, output format data and test case data through a pre-trained assembly code generation model to generate test codes, carrying out standardization processing on the test codes to generate assembly files, carrying out compiling processing on the assembly files to generate executable files corresponding to the test instructions, and testing the target processor based on the executable files to obtain processor test results. By adopting the method, comprehensive learning of the test instruction can be realized through the assembly code generation model, the intelligent generation of the full-coverage test code is realized, and the usability of the generated test code is further ensured.

Inventors

• SHI XIAOMING
• GOU PENGFEI
• ZHAO XING
• LI HUAQING

Assignees

• 上海灵睿智芯计算技术有限公司

Dates

Publication Date

20260508

Application Date

20260114

Claims (10)

1. 1. A method of processor testing, the method comprising: Obtaining test case data of a target processor, wherein the test case data comprises a test identifier, a test instruction type, a priority, a test instruction description and a generated prompt word; Processing test constraint data, output format data and test case data through a pre-trained assembly code generation model to generate test codes; And compiling the assembly file to generate an executable file corresponding to the test instruction, and testing the target processor based on the executable file to obtain a processor test result.
2. 2. The method according to claim 1, wherein the method further comprises: And performing parameter fine adjustment training processing on the target base model based on target training data to obtain a trained assembly code generation model, wherein the target training data set comprises a test instruction data set, a processor parameter set, an effective code file data set and an ineffective code file data set.
3. 3. The method according to claim 2, wherein the performing parameter fine tuning training processing on the target base model based on the target training data to obtain a trained assembly code generation model includes: Processing the test description data in the test instruction data set through the target base model to generate prediction instruction data; And calculating loss data based on the test instructions in the test instruction data set, the prediction instruction data and a preset loss function, and performing parameter fine adjustment on the target base model through the loss data and training weights corresponding to the test instruction data set to obtain a trained assembly code generation model.
4. 4. The method of claim 2, wherein the generating test code by processing test constraint data, output format data, and test case data through a pre-trained assembly code generation model comprises: Processing based on the test constraint data, the output format data and the test case data to generate target prompt data; and carrying out standardized processing on the test code data to generate an assembly file.
5. 5. The method of claim 3, wherein generating the hint words includes positive hint words and/or negative hint words, wherein processing based on test constraint data, output format data, and the test case data to generate target hint data includes: Generating instruction constraint data based on the instruction coverage, the test case data and the test constraint data, and processing based on the randomly generated seed identification, the instruction constraint data and the output format data to generate target prompt data.
6. 6. The method of claim 1, wherein the target processor is an analog processor, and wherein the testing the target processor based on the executable file results in a processor test result comprising: Executing the executable file in the simulation processor to obtain a simulation test result; if the simulation test result is a failure result, adding the test code and the test case to an invalid code file data set, and re-executing the steps of processing the test constraint data, the output format data and the test case data to generate a test code under the condition that a termination condition is not met; If the simulation test result is a successful result, testing the real processor through the executable file to obtain a real test result; and if the real test result is a failure result, updating the invalid code file data set based on a failure reason and a test code corresponding to the failure result.
7. 7. A processor testing apparatus, the apparatus comprising: The first acquisition module is used for acquiring test case data of the target processor, wherein the test case data comprises a test identifier, a test instruction type, a priority, a test instruction description and a generated prompt word; The first generation module is used for processing the test constraint data, the output format data and the test case data through a pre-trained assembly code generation model to generate test codes; and the second generation module is used for compiling the assembly file, generating an executable file corresponding to the test instruction, and testing the target processor based on the executable file to obtain a processor test result.
8. 8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1 to 6 when the computer program is executed.
9. 9. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 6.
10. 10. A computer program product comprising a computer program, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 6.

Description

Processor test method, apparatus, computer device, readable storage medium, and program product Technical Field The present application relates to the field of processor verification technology, and in particular, to a processor test method, apparatus, computer device, computer readable storage medium, and computer program product. Background With the rapid development of the field of electronic devices, a large number of processors are presented, each of which needs to be verified before being executed to ensure that the processor implementations conform to the ISA specifications of the open source instruction set architecture. Instruction set random test is a standard for instruction level verification, and is characterized by generating a random instruction sequence, running on a processor under test (DUT) and a reference model simultaneously, and comparing whether results (such as register values and memory states) are consistent. In the related art, verification is generally performed through handwriting rules and constraints, multiple redundant instructions can be randomly generated, and the processor cannot be covered comprehensively, so that the test efficiency of the processor is low. Disclosure of Invention In view of the foregoing, it is desirable to provide a processor testing method, apparatus, computer device, computer readable storage medium, and computer program product that can improve the testing efficiency. In a first aspect, the present application provides a processor test method, including: Obtaining test case data of a target processor, wherein the test case data comprises a test identifier, a test instruction type, a priority, a test instruction description and a generated prompt word; Processing test constraint data, output format data and test case data through a pre-trained assembly code generation model to generate test codes; And compiling the assembly file to generate an executable file corresponding to the test instruction, and testing the target processor based on the executable file to obtain a processor test result. In one embodiment, the method further comprises: And performing parameter fine tuning training processing on the target base model based on the target training data to obtain a trained assembly code generation model, wherein the target training data set comprises a test instruction data set, a processor parameter set, an effective code file data set and an ineffective code file data set. In one embodiment, the performing parameter fine tuning training processing on the target base model based on the target training data to obtain a trained assembly code generating model includes: Processing the test description data in the test instruction data set through the target base model to generate prediction instruction data; And calculating loss data based on the test instructions in the test instruction data set, the prediction instruction data and a preset loss function, and performing parameter fine adjustment on the target base model through the loss data and training weights corresponding to the test instruction data set to obtain a trained assembly code generation model. In one embodiment, the generating, by using a pre-trained assembly code generating model, the test constraint data, the output format data and the test case data to generate test codes includes: Processing based on the test constraint data, the output format data and the test case data to generate target prompt data; and carrying out standardized processing on the test code data to generate an assembly file. In one embodiment, the generating the prompting word includes positive prompting word and/or negative prompting word, the processing is performed based on the test constraint data, the output format data and the test case data to generate target prompting data, including: Generating instruction constraint data based on the instruction coverage, the test case data and the test constraint data, and processing based on the randomly generated seed identification, the instruction constraint data and the output format data to generate target prompt data. In one embodiment, the target processor is an analog processor, and the testing the target processor based on the executable file to obtain a processor test result includes: Executing the executable file in the simulation processor to obtain a simulation test result; if the simulation test result is a failure result, adding the test code and the test case to an invalid code file data set, and re-executing the steps of processing the test constraint data, the output format data and the test case data to generate a test code under the condition that a termination condition is not met; If the simulation test result is a successful result, testing the real processor through the executable file to obtain a real test result; and if the real test result is a failure result, updating the invalid code file data set based on a failure reason and a test code