CN-121996490-A - SPD hub chip testing method, device, equipment and medium

CN121996490ACN 121996490 ACN121996490 ACN 121996490ACN-121996490-A

Abstract

The application relates to a test method, a test device, test equipment and a test storage medium of an SPD hub chip. If it is determined that an SPD hub chip to be tested is placed in a replaceable limit frame of a test seat, and communication connection is established between the SPD hub chip to be tested and an upper computer, setting target environment parameters, initializing the SPD hub chip to be tested, wherein the upper computer is in communication connection with the test seat, writing preset test data into an EEPROM of the SPD hub chip based on the target environment parameters, then performing read-back comparison, generating static verification data, wherein the static verification data are used for judging static storage reliability of the SPD hub chip to be tested in a current environment, performing continuous read-write operation on the SPD hub chip to be tested, obtaining a dynamic pressure test data set, and generating a test result of the SPD hub chip to be tested based on the static verification data and the dynamic pressure test data set.

Inventors

MA YUNLE
YANG HAIYANG
HUANG QIURONG

Assignees

深圳市金泰克半导体有限公司

Dates

Publication Date: 20260508
Application Date: 20251230

Claims (10)

1. The method for testing the SPD hub chip is characterized by comprising the following steps of: If the SPD hub chip to be tested is determined to be placed in the replaceable limiting frame of the test seat, and communication connection is established between the SPD hub chip to be tested and the upper computer, setting target environment parameters and initializing the SPD hub chip to be tested, wherein the upper computer is in communication connection with the test seat; Based on the target environment parameters, writing preset test data into the EEPROM of the SPD hub chip, and then performing readback comparison to generate static verification data, wherein the static verification data is used for judging the static storage reliability of the SPD hub chip to be tested in the current environment; Performing continuous read-write operation on the SPD hub chip to be tested to obtain a dynamic pressure test data set; and generating a test result of the SPD hub chip to be tested based on the static verification data and the dynamic pressure test data set.
2. The method for testing the SPD hub chip of claim 1, wherein initializing the SPD hub chip to be tested comprises: Sending a configuration command to the SPD hub chip to be tested so as to enable the SPD hub chip to be tested to enter a ready mode; And executing full address erasing operation on the EEPROM inside the SPD hub chip so as to enable the SPD hub chip to be tested to be in an initial empty state.
3. The method for testing the SPD hub chip according to claim 1, wherein the writing back read comparison is performed after writing preset test data into the EEPROM of the SPD hub chip based on the target environmental parameter, and generating static verification data comprises: Generating a test data packet containing a random number and a preset mode sequence according to the target environment parameters, writing the test data packet into an EEPROM of the SPD hub chip to be tested, and recording a time stamp of a writing operation; after the writing operation is finished, reading data in a corresponding address range from the EEPROM, and comparing the reading result with the test data packet byte by byte to obtain a comparison result; and generating static verification data based on the comparison result and the time stamp.
4. The method for testing the SPD hub chip of claim 3, wherein the reading data of the corresponding address range from the EEPROM, comparing the read result with the test data packet byte by byte to obtain a comparison result, comprises: Initiating a read command to the SPD hub chip to be tested, and determining the address range which is the same as the address range of the write operation; acquiring readback data stored in the EEPROM according to the address range; comparing the read-back data with the data at the corresponding position in the original test data packet one by one according to the byte sequence, and determining the number of unmatched bytes and the address offset of the unmatched bytes; And generating a structured comparison result according to the number of the unmatched bytes and the address offset.
5. The method for testing the SPD hub chip according to claim 1, wherein the performing continuous read/write operations on the SPD hub chip to be tested to obtain a dynamic pressure test data set comprises: Circularly initiating continuous writing and reading instructions to the EEPROM of the SPD hub chip to be tested according to the preset frequency and address sequence; After each read-write operation is completed, the communication response state, the data consistency result and the operation time consumption are recorded in real time; caching the communication response state, the data consistency result and the operation time consumption into an original pressure log according to the time sequence; and extracting abnormal events, time sequence fluctuation and error rate indexes based on the original pressure log, and generating a dynamic pressure test data set.
6. The method of testing the SPD hub chip of claim 5, wherein the generating test results of the SPD hub chip under test based on the static verification data and the dynamic pressure test data set comprises: Judging whether the SPD hub chip to be tested has data retention errors or not according to the static verification data; if not, evaluating whether communication abnormality occurs in the SPD hub chip to be tested in the continuous reading and writing process according to the dynamic pressure test data set; If not, generating a test result which represents that the test passes, and if so, generating a test result which represents that the test fails.
7. The method of testing an SPD hub chip of claim 1, further comprising: And correlating the test result with the identification of the SPD hub chip to be tested, and storing the correlation result in a preset path.
8. A test apparatus of an SPD hub chip, the apparatus comprising a module to perform the test method of an SPD hub chip of any one of claims 1 to 7.
9. The electronic equipment is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus; A memory for storing a computer program; A processor, configured to implement the method for testing the SPD hub chip according to any one of claims 1 to 7 when executing a program stored on a memory.
10. A computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the method of testing an SPD hub chip according to any one of claims 1 to 7.

Description

SPD hub chip testing method, device, equipment and medium Technical Field The present application relates to the field of chip testing technologies, and in particular, to a method, an apparatus, a device, and a storage medium for testing an SPD hub chip. Background The SPD hub chip is used for managing Serial Presence Detection (SPD) information access of a plurality of memory modules, and the EEPROM integrated inside the SPD hub chip is required to reliably store configuration data under various environmental conditions. At present, the industry generally relies on expensive ATE (automatic test equipment) to carry out reliability verification on an SPD hub chip, but the method can finish the test, but the ATE platform has high hardware and software cost, is difficult to be deployed in a large scale in a production line or a middle and small laboratory, and the traditional test is mostly carried out in a conventional environment, lacks simulation of actual working conditions in other environments and the like, and cannot accurately evaluate the data holding capacity and communication stability of the chip in a real use environment. Therefore, providing a technical solution capable of accurately evaluating the data retention capability and communication stability of a chip in a real use environment has become a technical problem to be solved by those skilled in the art. It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art. Disclosure of Invention In view of the above, the present application provides a method, an apparatus, a device and a storage medium for testing an SPD hub chip, which aims to solve the above technical problems. In a first aspect, the present application provides a method for testing an SPD hub chip, the method comprising: If the SPD hub chip to be tested is determined to be placed in the replaceable limiting frame of the test seat, and communication connection is established between the SPD hub chip to be tested and the upper computer, setting target environment parameters and initializing the SPD hub chip to be tested, wherein the upper computer is in communication connection with the test seat; Based on the target environment parameters, writing preset test data into the EEPROM of the SPD hub chip, and then performing readback comparison to generate static verification data, wherein the static verification data is used for judging the static storage reliability of the SPD hub chip to be tested in the current environment; Performing continuous read-write operation on the SPD hub chip to be tested to obtain a dynamic pressure test data set; and generating a test result of the SPD hub chip to be tested based on the static verification data and the dynamic pressure test data set. In a second aspect, the present application provides a testing apparatus for an SPD hub chip, where the testing apparatus for an SPD hub chip includes a module that performs the testing method for an SPD hub chip described above. In a third aspect, the present application provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus; A memory for storing a computer program; And the processor is used for realizing the steps of the testing method of the SPD hub chip according to any one embodiment of the first aspect when executing the program stored in the memory. In a fourth aspect, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method for testing an SPD hub chip according to any one of the embodiments of the first aspect. Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages: According to the application, the low-cost test platform is constructed, the target environment parameters are applied to the SPD hub chip to be tested in the replaceable limit frame, and the static storage reliability and the dynamic communication robustness of the SPD hub chip under the real working condition are evaluated by combining the static writing-reading verification and the dynamic continuous reading-writing pressure test, so that the ATE equipment is not required to be relied on, the hardware cost is low, the batch replication can be realized, the comprehensive test result is generated by fusing the static verification data and the dynamic pressure test data set, the test coverage is improved, the problems of high cost and weak test environment simulation capability in the prior art are solved, and a practical solution is provided for the reliability