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CN-121996494-A - Universal serial bus power supply device and method for detecting abnormal hard reset

CN121996494ACN 121996494 ACN121996494 ACN 121996494ACN-121996494-A

Abstract

The invention provides a universal serial bus power supply device and a method for detecting abnormal hard reset, the apparatus includes a bit detector, a packet start period counter, a reset detector, and a flag generator. The bit detector receives and detects an input data signal and outputs a preamble acknowledgement signal having a first level in response to a preamble group in the input data signal. The packet start period counter starts counting when the preamble acknowledge signal has the second level, and outputs a packet start enable signal having the first level. The reset detector receives and judges whether the input data signal has a code related to a hard reset to output an abnormal hard reset signal and a K code acknowledge signal. The flag generator receives the packet start enable signal, the abnormal hard reset signal, the K code acknowledge signal and the reset enable signal to output the abnormal hard reset flag to the event recorder.

Inventors

  • CHEN ZHIMING

Assignees

  • 新唐科技股份有限公司

Dates

Publication Date
20260508
Application Date
20250403
Priority Date
20241105

Claims (10)

  1. 1. A universal serial bus power supply apparatus, comprising: A bit detector for receiving and detecting an input data signal and enabling a preamble acknowledge signal in response to a preamble group in the input data signal; A packet start period counter configured to start counting when the preamble confirm signal is disabled and to enable a packet start enable signal; a reset detector for receiving and judging whether the input data signal has a code related to hard reset to output an abnormal hard reset signal and a K code acknowledge signal, and A flag generator for receiving the packet start enable signal, the abnormal hard reset signal, the K code acknowledge signal and a reset enable signal to output an abnormal hard reset flag to an event recorder, Wherein in response to the abnormal hard reset signal being disabled, the flag generator disables the abnormal hard reset flag and the disabled abnormal hard reset flag represents that a hard reset event is not present, and Wherein the start of packet period counter disables the start of packet enable signal in response to the preamble acknowledgement signal being enabled or in response to the start of packet period counter counting to be greater than a predetermined value.
  2. 2. The universal serial bus power supply of claim 1, wherein the bit detector comprises: a bus idle detector configured to enable a bus idle signal in response to a bus idle bit group in the input data signal, and A bit comparator is configured to enable the preamble acknowledgement signal in response to the preamble bit set in the input data signal.
  3. 3. The universal serial bus power supply of claim 1, wherein the reset detector comprises: a K code comparator configured to compare the input data signal with a normal hard reset code when the preamble acknowledge signal is disabled and the packet start enable signal is enabled, wherein the K code comparator enables the K code acknowledge signal in response to the comparison result being the same, and An abnormal hard reset detector configured to compare the input data signal with the normal hard reset code when the preamble confirm signal is disabled, wherein the abnormal hard reset detector enables the abnormal hard reset signal in response to the comparison result being the same.
  4. 4. The universal serial bus power supply of claim 1, wherein the flag generator is configured to: responsive to the preamble confirm signal being disabled, determining whether the abnormal hard reset signal is enabled; determining whether the packet start enable signal is enabled in response to the abnormal hard reset signal being enabled, and In response to the packet initiation enable signal being enabled, the abnormal hard reset flag is enabled and output to the event recorder.
  5. 5. The universal serial bus power supply of claim 4 wherein the operation of the flag generator to determine whether the abnormal hard reset signal is enabled further comprises: In response to the abnormal hard reset signal not being enabled, the flag generator disables the abnormal hard reset flag and outputs to the event recorder.
  6. 6. A universal serial bus power unit as defined in claim 4, wherein, the operation of the flag generator to determine whether the packet start enable signal is enabled further comprises: in response to the packet start enable signal not being enabled, the flag generator determines whether the K code acknowledge signal and the reset enable signal are enabled and disabled, respectively, and In response to the K code acknowledge signal and the reset enable signal being enabled and disabled, respectively, the flag generator disables the abnormal hard reset flag and outputs to the event recorder.
  7. 7. The universal serial bus power supply of claim 6 wherein the operation of the flag generator to determine whether the K code acknowledge signal and the reset enable signal are enabled and disabled, respectively, further comprises: In response to the K code acknowledge signal and the reset enable signal not being enabled and disabled, respectively, the flag generator determines whether the reset enable signal is enabled or not, and In response to the reset enable signal being enabled, the flag generator enables the abnormal hard reset flag and outputs to the event recorder.
  8. 8. The universal serial bus power supply of claim 7 wherein the operation of the flag generator to determine whether the reset enable signal is enabled further comprises: In response to the reset enable signal not being enabled, the flag generator disables the abnormal hard reset flag and outputs to the event recorder.
  9. 9. A method of detecting an abnormal hard reset, comprising: disabling a preamble acknowledgement signal in response to an input data signal having no preamble set; in response to the preamble acknowledge signal being disabled, starting counting by a start of packet period counter and enabling a start of packet enable signal; Generating a K code acknowledge signal and an abnormal hard reset signal in response to the preamble acknowledge signal and the packet start enable signal, and Outputting an abnormal hard reset flag to an event recorder in response to the packet start enable signal, the K code acknowledge signal, the abnormal hard reset signal and a reset enable signal, Wherein the start of packet enable signal is disabled in response to the start of packet period counter counting greater than a predetermined value or in response to the preamble acknowledgement signal being enabled, and Wherein the abnormal hard reset flag is enabled in response to the abnormal hard reset signal and the packet start enable signal being enabled.
  10. 10. The method of detecting an abnormal hard reset of claim 9, further comprising: disabling the abnormal hard reset flag in response to the abnormal hard reset signal being disabled; in response to the abnormal hard reset signal, the packet start enable signal and the K-code acknowledge signal being enabled and the reset enable signal being disabled, disabling the abnormal hard reset flag, or The abnormal hard reset flag is enabled in response to the abnormal hard reset signal, the packet start enable signal, and the reset enable signal being enabled.

Description

Universal serial bus power supply device and method for detecting abnormal hard reset Technical Field The present invention relates to a universal serial bus (universal serial bus; USB) Powered Device (PD) device, and more particularly, to a USB PD device that can detect abnormal hard reset events and a method for detecting abnormal hard reset events. Background In universal serial bus (universal serial bus; USB) power-down (PD) testing or in practical use of USB PD devices, the transmitted packet sequence typically has a normal hard reset event. In addition, the transmission may be subject to interference (e.g., noise) such that the transmitted packet sequence is bit-inverted due to the interference, which may result in an abnormal hard reset event. Thus, there is a need for a solution that allows a USB PD device to make a hard reset when a normal hard reset event occurs while ignoring the presence of an abnormal hard reset event. Disclosure of Invention According to some embodiments of the present disclosure, a universal serial bus power supply device is provided, which includes a bit detector, a start-of-packet period counter, a reset detector, and a flag generator. The bit detector receives and detects an input data signal and outputs a preamble acknowledge signal having a first level in response to a preamble group in the input data signal. The packet start period counter is configured to start counting when the preamble acknowledgement signal has a second level, and output a packet start enable signal having the first level. The reset detector receives and judges whether the input data signal has codes related to hard reset so as to output an abnormal hard reset signal and a K code confirmation signal. The flag generator receives the packet start enable signal, the abnormal hard reset signal, the K code acknowledge signal and a reset enable signal to output an abnormal hard reset flag to an event recorder. Wherein, in response to the abnormal hard reset signal having the second level, the flag generator outputs an abnormal hard reset flag having the second level, and the abnormal hard reset flag having the second level indicates that the hard reset event is not present. The preamble confirmation signal is provided with a first level, or the packet start period counter is provided with a second level and is used for counting to be larger than a preset value. Wherein the first level is greater than the second level. According to some embodiments of the present disclosure, there is further provided a method of detecting an abnormal hard reset, comprising generating a preamble acknowledge signal having a first level in response to an input data signal without a preamble group, starting counting by a packet start period counter in response to the preamble acknowledge signal having the first level and generating a packet start enable signal having a second level, generating a K-code acknowledge signal and an abnormal hard reset signal in response to the preamble acknowledge signal and the packet start enable signal, and outputting an abnormal hard reset flag to an event recorder in response to the packet start enable signal, the K-code acknowledge signal, the abnormal hard reset signal and a reset enable signal. Wherein the second level is greater than the first level. Wherein the packet start enable signal having the first level is generated in response to the packet start period counter counting to be greater than a predetermined value or in response to the preamble confirm signal having the second level. Wherein the abnormal hard reset flag having the second level is generated in response to the abnormal hard reset signal and the packet start enable signal having the second level. By the USB PD device and the method for detecting abnormal hard reset as described above, the detection of a hard reset event can be performed on the entire packet. In addition, the USB PD device may determine whether the hard reset event is an abnormal hard reset event by determining that the hard reset event is detected during or outside of the SOP period. In addition, the USB PD device described above may further determine the SOP mode of the transmitted packet according to the start code of the packet transmitted in the SOP period, and compare the SOP mode with the current device setting. If the comparison results are not consistent, the USB PD device does not perform the hard reset when detecting the hard reset event. The design can make the judgment of the abnormal hard reset event by the USB PD device more reliable, and effectively filters unnecessary abnormal hard reset events so as to avoid unnecessary hard reset of the system caused by the interference of the packet in the transmission process, thereby influencing the subsequent transmission or authentication. Drawings Fig. 1 is a schematic diagram of a packet specification according to an embodiment of the present disclosure. FIG. 2 is a block flow diagram of a unive