CN-121996569-A - Power line carrier communication data processing method and device

CN121996569ACN 121996569 ACN121996569 ACN 121996569ACN-121996569-A

Abstract

The invention relates to the technical field of power line carrier communication, in particular to a power line carrier communication data processing method and a device, wherein the method comprises the steps of mapping a plurality of target data through a first mapping rule and writing the mapped target data into a plurality of memories; the method comprises the steps of mapping logic read addresses according to a first mapping rule in a reading stage of each iterative operation period to obtain physical read addresses, reading corresponding target data according to the physical read addresses, carrying out fast Fourier calculation according to a plurality of parallel base 4 operation modules to obtain calculation results, writing the calculation results back to original physical addresses to cover original data according to the first mapping rule in a writing stage of a non-last iterative operation period, generating physical writing addresses corresponding to the calculation results according to a second mapping rule in a writing stage of a last iterative operation period, and writing the calculation results to the corresponding physical writing addresses. The invention effectively improves the calculation speed and the read-write speed, shortens the processing time and ensures the timeliness.

Inventors

Wang Kunshou
ZHU ZHONGYI
LIN XIONGXIN

Assignees

苏州门海微电子科技有限公司

Dates

Publication Date: 20260508
Application Date: 20260106

Claims (10)

1. The power line carrier communication data processing method is characterized by comprising the following steps: address mapping is carried out on a plurality of target data stored according to an original natural sequence through a first mapping rule, and then the target data are written into a plurality of memories, so that physical addresses of a plurality of target data read by a plurality of parallel base 4 operation modules are distributed in different memories; Mapping the logic read addresses generated by the plurality of parallel base 4 operation modules according to the first mapping rule in the read stage of each iterative operation period to obtain physical read addresses, and carrying out data reading on the corresponding plurality of target data according to the physical read addresses, wherein the physical read addresses are configured to distribute the physical addresses of the plurality of target data to be read in a single read stage in different memories; Performing fast Fourier computation according to a plurality of parallel base 4 operation modules to obtain computation results of a plurality of target data, wherein the computation results of the last iteration operation period are arranged according to a bit reverse order; in the writing stage of the iteration operation period not the last time, writing the calculation result back to the original physical address according to the first mapping rule, and covering the original data before the calculation of the original physical address; And generating a physical write-in address corresponding to the calculation result according to a second mapping rule in the write-in stage of the last iterative operation period, and writing the calculation result into the corresponding physical write-in address, wherein the second mapping rule is configured to adjust the mapping relation in the group of the memories and optimize the distribution of the calculation result in a plurality of memories so as to realize parallel conflict-free access of a plurality of calculation results in a single read-in stage when the calculation result is read according to the original natural sequence.
2. The power line carrier communication data processing method according to claim 1, wherein address mapping is performed on a plurality of target data stored according to an original natural order by a first mapping rule and then written into a plurality of memories, comprising the steps of: calculating the mapped physical addresses according to the logical sequence numbers of the target data in the original natural sequence through the first mapping rule, wherein the physical addresses comprise storage group indexes, storage indexes and storage address indexes; and storing the target data into the physical address corresponding to the logic sequence number.
3. The power line carrier communication data processing method according to claim 2, wherein calculating the mapped physical address by the first mapping rule according to a logical sequence number of the target data in the original natural sequence, comprises the steps of: Dividing the logic sequence number into a plurality of fields by binary representation according to fixed bit numbers; Calculating the storage group index through a modulo arithmetic according to the field sum of a first field group of the logic sequence number, wherein the first field group comprises a first preset number of high-order fields; calculating the memory index through a modulo algorithm according to the sum of fields of a second field group of the logic sequence number, wherein the second field group comprises the first field group and a low-order field adjacent to the first field group; and taking a second preset number of digits of the ten-digit binary representation of the logic sequence number as the storage address index.
4. A power line carrier communication data processing method according to claim 3, characterized in that: the number of the base 4 operation modules, the number of the storage groups and the number of the memories of each storage group are all set to be 4, and the iterative operation period is an iterative period of parallel 4 base 4 fast Fourier computations; calculating the storage group index through a modulo arithmetic according to the field sum of the first field group of the logic sequence number, wherein the storage group index is expressed as: , in the formula, For the storage group index to be stored, The first of the logical sequence numbers being a binary representation Bit sum of The bit is used to indicate the position of the bit, 、、 And For the first field set, " "Means summing the corresponding fields; Calculating the memory index according to the sum of the fields of the second field group of the logic sequence number through a modulo arithmetic, wherein the memory index is expressed as: , in the formula, For the index of the memory to be described, The lower fields being adjacent to the first field set; The upper 6 bits of the logic sequence number are used as the storage address index and expressed as 。
5. The power line carrier communication data processing method according to claim 1, wherein, in a writing stage of the iterative operation cycle other than the last time, writing the calculation result back to the original physical address according to the first mapping rule, and overlaying the original data before the calculation of the original physical address, comprising the steps of: Acquiring the logic reading address of the target data corresponding to the calculation result of the current iterative operation period; Calculating the logic reading address according to the first mapping rule to obtain the original physical address consistent with the corresponding physical reading address; And writing the calculation result into the original physical address according to the corresponding original physical address, and covering the original data of the original physical address.
6. The power line carrier communication data processing method according to claim 1, wherein in a writing stage of the iterative operation cycle at the last time, generating a physical writing address corresponding to the calculation result according to a second mapping rule, and writing the calculation result into the corresponding physical writing address, comprising the steps of: acquiring the logic reading address of the target data corresponding to the calculation result of the last iterative operation period; The physical write address is configured to distribute the physical addresses of the calculation results of a plurality of target data to be read in a single read stage in different memories, wherein the physical write address comprises a write storage group index, a write storage index and a write storage address index; and writing the calculation result according to the corresponding physical writing address.
7. The method for processing the power line carrier communication data according to claim 6, wherein calculating the logical read address according to the second mapping rule to obtain the physical write address comprises the steps of: Dividing the logic read address into a plurality of fields by binary representation with a fixed number of bits; calculating the index of the written storage group through a modulo arithmetic according to the sum of fields of a first field group of the logic read address, wherein the first field group comprises a first preset number of a plurality of high-order fields; Calculating the index of the write memory through a modulo arithmetic according to the sum of fields of a third field group of the logical read address, wherein the third field group comprises the first field group, a highest-order field in the first field group and a low-order field adjacent to the first field group; And taking a second preset number of digits of the ten-bit binary representation of the logic read address as the index of the write storage address.
8. The power line carrier communication data processing method according to claim 7, wherein: calculating the written memory index according to the sum of the fields of the third field group of the logic sequence number by a modulo arithmetic, wherein the written memory index is expressed as follows: , in the formula, For the writing of the memory index, The first of the logical read addresses being a binary representation Bit sum of The bit is used to indicate the position of the bit, For the most significant field in the first field set, " "Means summing the corresponding fields.
9. The power line carrier communication data processing method according to claim 1, further comprising the step of, before address mapping the plurality of target data stored in accordance with the original natural order by the first mapping rule and writing the mapped target data into the plurality of memories: Calculating the total iteration times of the iteration operation period according to the total number of the target data, wherein the total iteration times are expressed as follows: , in the formula, For the total number of iterations to be described, Is the total number of the target data; according to the total iteration times, respectively calculating the number of butterfly operation groups and the data index difference among the butterflies in each iteration operation period, wherein the data index difference is expressed as: , , in the formula, Is the first The number of groups of butterfly operations for each of the iterative operation cycles, As a loop variable for the iterative operation period, , Is the first The inter-butterfly data index differences of the iterative operation periods; Calculating the inter-butterfly data index difference according to the inter-butterfly data index difference, wherein the inter-butterfly data index difference is expressed as: , in the formula, Is the first The data index differences in the butterflies of the iterative operation periods; And determining the logic reading address according to the butterfly operation group number, the inter-butterfly data index difference and the intra-butterfly data index difference.
10. A power line carrier communication data processing apparatus applied to the power line carrier communication data processing method according to any one of claims 1 to 9, characterized by comprising: The first module is used for carrying out address mapping on a plurality of target data stored according to an original natural sequence and writing the target data into a plurality of memories through a first mapping rule so that physical addresses of a plurality of target data read by a plurality of parallel base 4 operation modules are distributed in different memories; The second module is used for mapping the logic read addresses generated by the plurality of parallel base 4 operation modules according to the first mapping rule in the read stage of each iterative operation period to obtain physical read addresses, and carrying out data reading on a plurality of corresponding target data according to the physical read addresses, wherein the physical read addresses are configured to distribute the physical addresses of the plurality of target data which need to be read in a single read stage in different memories; The third module is used for carrying out fast Fourier computation according to the plurality of parallel base 4 operation modules to obtain computation results of a plurality of target data, wherein the computation results of the last iteration operation period are arranged according to a bit reverse order; A fourth module, configured to write the calculation result back to the original physical address according to the first mapping rule in a writing stage of the iteration operation cycle not last time, and cover the original data before calculation of the original physical address; And a fifth module, configured to generate a physical write address corresponding to the calculation result according to a second mapping rule in a write stage of the iterative operation cycle at the last time, and write the calculation result into the corresponding physical write address, where the second mapping rule is configured to adjust a mapping relationship in a group of the memories, and optimize distribution of the calculation result in a plurality of memories, so that parallel collision-free access of a plurality of calculation results is realized in a single read stage when the calculation result is read according to the original natural sequence.

Description

Power line carrier communication data processing method and device Technical Field The present invention relates to the field of power line carrier communication technologies, and in particular, to a method and an apparatus for processing power line carrier communication data. Background In the existing power line carrier communication system, modulation of signals is mainly realized by an Orthogonal Frequency Division Multiplexing (OFDM) technology, and time-frequency conversion of signals is realized by fast fourier transform or inverse fast fourier transform (FFT/IFFT). The data size of the power line carrier communication in the fast fourier computation is relatively large, typically 1024. The large data volume tends to increase data processing time, and further data loss occurs, resulting in communication failure. In the prior art, a mode that 1 base 4 operation module reads and writes data from and into 4 single-port read-write memories in parallel is mainly adopted. The calculation speed and the read-write speed of the mode are relatively slow, so that the data processing time of the fast Fourier calculation is long, and the requirements of the next generation of power line carrier communication cannot be met. Disclosure of Invention The method and the device for processing the power line carrier communication data at least solve the problem of long processing time required by the existing data processing method, effectively improve the calculation speed and the read-write speed, shorten the time required by processing and meet the requirement of the power line carrier communication on timeliness. In a first aspect, the invention provides a power line carrier communication data processing method, which comprises the steps of performing address mapping on a plurality of target data stored according to an original natural sequence, writing the target data into a plurality of memories through a first mapping rule, enabling physical addresses of the target data read by a plurality of parallel base 4 operation modules to be distributed in different memories, mapping logical read addresses generated by the plurality of parallel base 4 operation modules according to the first mapping rule in a reading stage of each iterative operation cycle to obtain physical read addresses, performing data reading on the corresponding plurality of target data according to the physical read addresses, wherein the physical read addresses are configured to distribute the physical addresses of the target data required to be read in a single reading stage in different memories, performing fast Fourier computation according to the plurality of parallel base 4 operation modules to obtain computation results of the target data, performing mapping on the logical read addresses generated by the plurality of parallel base 4 operation modules according to the first mapping rule in a non-order-sequence, writing the physical read addresses into the corresponding first mapping rule in a first iterative operation cycle, optimizing the physical address in the first iterative operation cycle, writing the physical address into the corresponding memory according to the first iterative operation cycle, and writing the physical address into the first iterative operation cycle in the first iterative operation cycle, and optimizing the write-back computation results into the corresponding memory according to the first iterative operation rule, so that when the subsequent reading is performed according to the original natural sequence, parallel conflict-free access of a plurality of calculation results is realized in a single reading stage. In one embodiment of the invention, a plurality of target data stored according to an original natural sequence are written into a plurality of memories after address mapping is carried out through a first mapping rule, and the method comprises the steps of calculating mapped physical addresses through the first mapping rule according to logic sequence numbers of the target data in the original natural sequence, wherein the physical addresses comprise storage group indexes, storage indexes and storage address indexes, the memories are divided into a plurality of storage groups, each storage group comprises 4 memories, each memory comprises a plurality of storage addresses, and the target data are stored into the physical addresses corresponding to the logic sequence numbers. In one embodiment of the invention, the physical address mapped according to the logical sequence number of the target data in the original natural sequence is calculated through the first mapping rule, and the method comprises the steps of dividing the logical sequence number into a plurality of fields through binary representation according to fixed bit numbers, calculating the storage group index through a modulo algorithm according to the sum of fields of a first field group of the logical sequence number, wherein the first field group