CN-121996570-A - AWG waveform data storage method based on DDR architecture

CN121996570ACN 121996570 ACN121996570 ACN 121996570ACN-121996570-A

Abstract

The invention relates to the technical field of data storage, and particularly discloses an AWG waveform data storage method based on a DDR (double data rate) framework, which comprises the following steps of waveform data storage configuration, namely, classifying storage and identification of test excitation waveform data are realized by logically layering and dividing DDR storage space and configuring head information descriptors containing data length information for each waveform sub-block; and (3) dynamic waveform scheduling, namely after the upper computer issues the initial base address of the unified waveform data block, the FPGA calculates the initial address of the waveform data of each channel according to the initial base address, and the waveform data of each channel is transmitted to the corresponding DAC unit in parallel by combining the waveform data length to generate a test excitation waveform. The DDR memory space is logically divided into multiple independent areas, multiple waveform sub-blocks are divided in each area, and the pre-storage and the quick positioning of multiple test excitation waveforms are realized by matching with a special head information descriptor, so that the limitation that the traditional scheme only supports a single test mode is solved.

Inventors

CHEN JIAHAO
YANG AIMIN
ZHANG YUE
Ji Runzai
ZHANG QI

Assignees

悦芯科技股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260109

Claims (10)

1. The AWG waveform data storage method based on the DDR architecture is characterized by comprising the following steps of: The waveform data storage configuration is that the DDR storage space is logically divided in layers, and head information descriptors containing data length information are configured for each waveform sub-block, so that the classification storage and identification of test excitation waveform data are realized; and (3) dynamic waveform scheduling, namely after the upper computer issues the initial base address of the unified waveform data block, the FPGA calculates the initial address of the waveform data of each channel according to the initial base address, and the waveform data of each channel is transmitted to the corresponding DAC unit in parallel by combining the waveform data length to generate a test excitation waveform.
2. The AWG waveform data storage method based on DDR architecture of claim 1, wherein the waveform data storage configuration comprises the specific steps of: logically dividing the DDR memory space into a plurality of independent memory areas corresponding to the physical output channels one by one; In each independent storage area, a plurality of waveform sub-blocks are further divided and used for respectively storing different test excitation waveform data; A header descriptor is configured for each of the waveform sub-blocks.
3. The AWG waveform data storage method based on DDR architecture of claim 2, wherein the dynamic waveform scheduling specific steps are as follows: The upper computer transmits a unified waveform data block initial base address to the FPGA; The FPGA calculates head information descriptor addresses corresponding to all physical output channels through fixed address offset according to a preset storage structure rule; The FPGA reads the head information descriptors of all channels through the DDR controller IP core, and calculates the waveform data initial address of the waveform sub-block corresponding to each channel according to the initial base address and the storage layout rule; The FPGA combines the waveform data initial address and the waveform data length information, and the waveform data of each channel is transmitted to the corresponding DAC unit in parallel through the DDR controller IP core and the internal logic to generate a test excitation waveform.
4. The AWG waveform data storage method based on DDR architecture of claim 3, wherein the number of independent storage areas is consistent with the number of physical output channels, and the size of each independent storage area is a fixed value or a configurable value.
5. The AWG waveform data storage method based on DDR architecture of claim 3, wherein the waveform sub-blocks in each independent storage area are of continuous storage structure or discontinuous storage structure.
6. The AWG waveform data storage method based on DDR architecture of claim 3, wherein the header descriptor occupies a storage space with a fixed size in DDR, and the header descriptor address corresponding to each channel is obtained by accumulating a uniform base address and a fixed offset.
7. The AWG waveform data storage method based on DDR architecture according to claim 3, wherein the FPGA reads waveform data in each independent storage area through an independent data path, so as to realize parallel output of multi-channel waveform data, and test excitation waveforms output by each channel do not interfere with each other.
8. The AWG waveform data storage method based on DDR architecture of claim 3, wherein the output engine of a single physical output channel dynamically jumps to any waveform sub-block in its dedicated independent memory area according to a sequence instruction, realizing switching of different test excitation waveforms without reloading waveform data.
9. The AWG waveform data storage method based on DDR architecture of claim 3, wherein the number of physical output channels is 8, the corresponding independent storage areas are CH1-CH8, respectively, and each waveform sub-block in the independent storage areas can store a plurality of different test excitation waveform data.
10. The AWG waveform data storage method based on DDR architecture of claim 2, wherein the header information descriptor includes waveform data length information of a corresponding waveform sub-block.

Description

AWG waveform data storage method based on DDR architecture Technical Field The invention relates to the technical field of data storage, in particular to an AWG waveform data storage method based on a DDR architecture. Background In FPGA application, large-capacity DDR SDRAM can be used as a waveform memory core, test excitation waveform data are preloaded into a memory, and during test, a DMA controller and custom logic in the FPGA directly read mass waveform data from the DDR stably and at high speed and convert the mass waveform data into analog signals through a high-precision DAC, so that a required test excitation waveform is generated. However, the prior art suffers from the significant disadvantage that DDR-based AWG schemes typically treat the entire DDR memory space as a whole, or simply allocate a single waveform memory area for each channel fixedly. When different test excitation needs to be switched by a test task, the system cannot realize the rapid output and dynamic switching of multiple test excitation, so that the test efficiency is low, the adaptability of the system in multiple-scene and multiple-parameter test is severely limited, and the requirements of high-end chip test on concurrency and flexibility are difficult to meet. Disclosure of Invention The invention aims to provide an AWG waveform data storage method based on DDR architecture so as to solve the technical problems. The aim of the invention can be achieved by the following technical scheme: The AWG waveform data storage method based on the DDR framework comprises the following steps: The waveform data storage configuration is that the DDR storage space is logically divided in layers, and head information descriptors containing data length information are configured for each waveform sub-block, so that the classification storage and identification of test excitation waveform data are realized; and (3) dynamic waveform scheduling, namely after the upper computer issues the initial base address of the unified waveform data block, the FPGA calculates the initial address of the waveform data of each channel according to the initial base address, and the waveform data of each channel is transmitted to the corresponding DAC unit in parallel by combining the waveform data length to generate a test excitation waveform. As a further scheme of the invention, the waveform data storage configuration comprises the following specific steps: logically dividing the DDR memory space into a plurality of independent memory areas corresponding to the physical output channels one by one; In each independent storage area, a plurality of waveform sub-blocks are further divided and used for respectively storing different test excitation waveform data; A header descriptor is configured for each of the waveform sub-blocks. The method is characterized in that the specific steps of the dynamic waveform scheduling are as follows: The upper computer transmits a unified waveform data block initial base address to the FPGA; The FPGA calculates head information descriptor addresses corresponding to all physical output channels through fixed address offset according to a preset storage structure rule; The FPGA reads the head information descriptors of all channels through the DDR controller IP core, and calculates the waveform data initial address of the waveform sub-block corresponding to each channel according to the initial base address and the storage layout rule; The FPGA combines the waveform data initial address and the waveform data length information, and the waveform data of each channel is transmitted to the corresponding DAC unit in parallel through the DDR controller IP core and the internal logic to generate a test excitation waveform. As a further scheme of the invention, the number of the independent storage areas is consistent with the number of the physical output channels, and the size of each independent storage area is a fixed value or a configurable value. As a further scheme of the invention, the waveform sub-blocks in each independent storage area are of a continuous storage structure or a discontinuous storage structure. The invention further provides a scheme that the head information descriptors occupy a storage space with a fixed size in the DDR, and head information descriptor addresses corresponding to all channels are obtained through accumulation calculation of a unified base address and a fixed offset. As a further scheme of the invention, the FPGA reads waveform data in each independent storage area through an independent data channel to realize parallel output of multi-channel waveform data, and test excitation waveforms output by each channel are not interfered with each other. As a further scheme of the invention, an output engine of a single physical output channel dynamically jumps to any waveform sub-block in a dedicated independent storage area according to a sequence instruction, so that switching of different test ex