CN-121996571-A - Address mapping method, device, equipment and storage medium based on DDR interleaving

Abstract

A DDR interleaving-based address mapping method, device, equipment and storage medium relate to the field of computer storage and comprise the steps of sequentially mapping interleaving bits of basic address blocks through a lookup table to obtain target mapping addresses, calculating relative offsets of different basic address blocks in the same DDR according to the distribution quantity of sub-address blocks in a DDR channel x after interleaving of basic address blocks in a DDR channel y before interleaving and the sequence number of the basic address blocks, determining self-adaptive offsets among different DDR channels based on the quantity of sub-address blocks, mapped to the DDR channel x after interleaving, of all DDR channels before interleaving, and generating target addresses corresponding to the interleaved addresses based on top_addr_bit, target mapping addresses, relative offsets, self-adaptive offsets and target address bits corresponding to interleaving granularity, so that the addresses after interleaving to all DDRs are still sequentially arranged, and the read-write performance of the DDR is improved.

Inventors

• ZHOU YOU
• CHEN YOUHONG
• HAN MUHUA

Assignees

• 湖北芯擎科技股份有限公司

Dates

Publication Date

20260508

Application Date

20260410

Claims (10)

1. 1. The address mapping method based on DDR interleaving is characterized by comprising the following steps: Sequentially mapping the interleaving bits of the basic address block in the interleaved address through a lookup table to obtain a target mapping address in the basic address block, wherein the original values of the interleaving bits are in nonlinear distribution, and the table is used for storing one-to-one correspondence between all possible values of the interleaving bits and continuous sequential addresses; calculating the relative offset of different basic address blocks in the same DDR according to the number of sub address block distribution and the sequence number of the basic address blocks in the DDR channel y before interleaving and the DDR channel x after interleaving; Determining the self-adaptive offset between different DDR channels based on the number of sub address blocks of the DDR channel x mapped to the DDR channel x after interleaving of all DDR channels arranged in front of the DDR channel y before interleaving; Generating a target address corresponding to the interleaved address based on the bit top_addr_bit used to calculate the interleaving, the target mapping address, the relative offset, the adaptive offset, and a target address bit corresponding to the interleaving granularity.
2. 2. The DDR interleaving-based address mapping method of claim 1, wherein the generating a target address corresponding to the interleaved address based on the bits top_addr_bit used for calculating the interleaving, the target mapping address, the relative offset, the adaptive offset, and the target address bits corresponding to the interleaving granularity, comprises: Obtaining a processed address according to the target mapping address, the relative offset and the adaptive offset; And setting the top_addr_bit to 0, and combining the top_addr_bit with the processed address and the target address bit to obtain a target address corresponding to the interleaved address.
3. 3. The DDR interleave-based address mapping method of claim 2, wherein the calculation expression of the processed address is: ADDR_OUT(x)=ADDR_LUT+block_offset(y,x)+SN_offset(y,x) In the formula, ADDR_OUT (x) represents a processed address in the DDR channel x after interleaving, ADDR_LUT represents a target mapping address, (y, x) represents an address before interleaving belongs to an address space of the DDR channel y and an address after interleaving belongs to an address space of the DDR channel x, block_offset (y, x) represents a relative offset, and SN_offset (y, x) represents an adaptive offset.
4. 4. The DDR interleave-based address mapping method of claim 1, wherein the relative offset block_offset (y, x) is calculated as: block_offset(y,x)=K×const(y,x) Where (y, x) indicates that the address before interleaving belongs to the address space of the DDR channel y and the address after interleaving belongs to the address space of the DDR channel x, const (y, x) indicates the number of sub-address blocks where the basic address blocks in the DDR channel y before interleaving are interleaved into the DDR channel x after interleaving, and K indicates the sequence number of the basic address blocks.
5. 5. The DDR interleave-based address mapping method of claim 1, wherein the adaptive offset sn_offset (y, x) is calculated as: Wherein (y, x) represents that the address before interleaving belongs to the address space of the DDR channel y and the address after interleaving belongs to the address space of the DDR channel x, const (y, x) represents that the basic address blocks in the DDR channel y before interleaving are interleaved to the distribution number of sub address blocks in the DDR channel x after interleaving, S represents the particle size of the DDR, and the value of k is determined by the interleaving granularity.
6. 6. An address mapping device based on DDR interleaving is characterized in that, the address mapping device based on DDR interleaving comprises: The first processing module is used for carrying out sequential mapping operation on interleaving bits of a basic address block in the interleaved address through a lookup table to obtain a target mapping address in the basic address block, the original values of the interleaving bits are in nonlinear distribution, and the table is used for storing one-to-one correspondence between all possible values of the interleaving bits and continuous sequential addresses; The second processing module is used for calculating the relative offset of different basic address blocks in the same DDR according to the distribution quantity of the basic address blocks in the DDR channel y before interleaving and the sub address blocks in the DDR channel x after interleaving and the sequence numbers of the basic address blocks; the third processing module is used for determining the self-adaptive offset between different DDR channels based on the number of sub address blocks, which are mapped to the DDR channel x after interleaving, of all DDR channels arranged in front of the DDR channel y before interleaving; An address mapping module for generating a target address corresponding to the interleaved address based on the bit top_addr_bit used to calculate the interleaving, the target mapping address, the relative offset, the adaptive offset, and a target address bit corresponding to the interleaving granularity.
7. 7. The DDR interleave-based address mapping device of claim 6, wherein said address mapping module is specifically configured to: Obtaining a processed address according to the target mapping address, the relative offset and the adaptive offset; And setting the top_addr_bit to 0, and combining the top_addr_bit with the processed address and the target address bit to obtain a target address corresponding to the interleaved address.
8. 8. The DDR interleave-based address mapping device of claim 7, wherein the calculation expression of the processed address is: ADDR_OUT(x)=ADDR_LUT+block_offset(y,x)+SN_offset(y,x) In the formula, ADDR_OUT (x) represents a processed address in the DDR channel x after interleaving, ADDR_LUT represents a target mapping address, (y, x) represents an address before interleaving belongs to an address space of the DDR channel y and an address after interleaving belongs to an address space of the DDR channel x, block_offset (y, x) represents a relative offset, and SN_offset (y, x) represents an adaptive offset.
9. 9. A DDR interleave-based address mapping device comprising a processor, a memory and a DDR interleave-based address mapping program stored on the memory and executable by the processor, wherein the DDR interleave-based address mapping program, when executed by the processor, implements the steps of the DDR interleave-based address mapping method of any of claims 1 to 5.
10. 10. A computer readable storage medium, wherein a DDR interleave based address mapping program is stored on the computer readable storage medium, wherein the DDR interleave based address mapping program, when executed by a processor, implements the steps of the DDR interleave based address mapping method according to any of claims 1 to 5.

Description

Address mapping method, device, equipment and storage medium based on DDR interleaving Technical Field The application relates to the technical field of computer storage, in particular to an address mapping method, device and equipment based on DDR interleaving and a storage medium. Background In high performance computing systems, to increase memory bandwidth, a multi-channel DDR (DoubleDataRateSDRAM, double rate synchronous dynamic random access memory) memory architecture is typically employed. The CMN (CoherentMeshNetwork) bus acts as a coherent interconnect network provided by ARM company for implementing cache coherency in multiprocessor systems that supports multiple DDR interleaving modes, including, for example, 3DDR interleaving mode and 6DDR interleaving mode. It is noted that when using an interleaving pattern of 3DDR or 6DDR, the interleaved address removes topaddressbit (the high order address field, i.e., the address bit of the highest order in the physical address) of the corresponding pattern to ensure that addresses interleaved to different DDR can cover a continuous address space. In the related art, for a CMN bus, an interleaving formula corresponding to a 3DDR interleaving mode is SN= { ADDR [ k+2:k ] +ADDR [ k+5:k+3] +ADDR [ k+8:k+6] + ((top_addr_bit1 < < 1) |top_addr_bit0) } 3, and a formula corresponding to a 6DDR interleaving mode is ：SN={ADDR[k+2:k]+ADDR[k+5:k+3]+ADDR[k+8:k+6]+((top_addr_bit2<<2)|(top_addr_bit1<<1)|top_addr_bit0)}%6,, SN is an interleaving channel calculation result and represents a specific DDR channel number to which an address should be mapped, ADDR is a system address before interleaving (for example, if the system address is 40 bits, ADDR represents an address before interleaving), top_addr_bit0, top_addr_bit1 and top_addr_bit2 are bits selected according to DDR particle sizes (namely, DDR capacity sizes) and address allocation, so that the addresses to each DDR can be evenly distributed, wherein the top_addr_bit0 and the interleaving rule can be determined by a reference to an interleaving rule of the user. Although interleaving is realized by the above formula, the interleaved addresses can cover a continuous address space, but the addresses cannot be ensured to be arranged sequentially. In some application scenarios, the non-sequential address arrangement may cause the DDR controller to fail to fully utilize the burst transmission (bursttransfer) characteristics, so that the optimal bandwidth of the DDR is not achieved, for example, as shown in fig. 1, in the 6DDR interleaving mode, the first 512 addresses interleaved to DDR0 are arranged in a non-continuous and non-sequential manner, which reduces the memory access efficiency. Disclosure of Invention The application provides an address mapping method, device, equipment and storage medium based on DDR interleaving, which can solve the problem that the interleaved addresses cannot be arranged in sequence in the prior art. In a first aspect, an embodiment of the present application provides a DDR interleaving-based address mapping method, where the DDR interleaving-based address mapping method includes: Sequentially mapping the interleaving bits of the basic address block in the interleaved address through a lookup table to obtain a target mapping address in the basic address block, wherein the original values of the interleaving bits are in nonlinear distribution, and the table is used for storing one-to-one correspondence between all possible values of the interleaving bits and continuous sequential addresses; calculating the relative offset of different basic address blocks in the same DDR according to the number of sub address block distribution and the sequence number of the basic address blocks in the DDR channel y before interleaving and the DDR channel x after interleaving; Determining the self-adaptive offset between different DDR channels based on the number of sub address blocks of the DDR channel x mapped to the DDR channel x after interleaving of all DDR channels arranged in front of the DDR channel y before interleaving; Generating a target address corresponding to the interleaved address based on the bit top_addr_bit used to calculate the interleaving, the target mapping address, the relative offset, the adaptive offset, and a target address bit corresponding to the interleaving granularity. With reference to the first aspect, in an implementation manner, the generating, based on the bit top_addr_bit used to calculate the interleaving, the target mapping address, the relative offset, the adaptive offset, and the target address bit corresponding to the interleaving granularity, the target address corresponding to the interleaved address includes: Obtaining a processed address according to the target mapping address, the relative offset and the adaptive offset; And setting the top_addr_bit to 0, and combining the top_addr_bit with the processed address and the target address bit to obtain a targe