CN-121996572-A - Cache access control method and device

CN121996572ACN 121996572 ACN121996572 ACN 121996572ACN-121996572-A

Abstract

The application relates to the technical field of computers and provides a cache access control method and device, wherein the method comprises the steps of determining hit information during cache access; and when the hit information is that the cache access competition fails and the tag is not hit, directly sending a cache access request of the target data to the next level cache of the current cache. In the embodiment, when the cache access competition fails and the tag is not hit, the tag unit is directly accessed, so that the condition of the cache miss can be timely found, and a request is timely sent to the next-level cache.

Inventors

YANG RUIJIA

Assignees

成都群芯微电子科技有限公司

Dates

Publication Date: 20260508
Application Date: 20251229

Claims (15)

1. A cache access control method, the method comprising: Determining hit information during cache access; And when the hit information is that the cache access competition fails and the tag is not hit, directly sending a cache access request of the target data to the next level cache of the current cache.
2. The method as recited in claim 1, further comprising: optimizing the banks in the cache by: Dividing all cache lines in a cache into a plurality of cache groups according to a multi-path group association structure; Dividing the cache group into a plurality of data blocks according to the designated bit index of the virtual address; splitting a single cache line into a plurality of sub-data segments according to a preset byte number; Grouping the multi-path group connection structures according to the preset path number; and integrating the sub data segments of the cache lines of the corresponding paths according to the grouping of the multi-path group association structure to obtain the storage body with optimized granularity.
3. The method of claim 2, wherein the predetermined number of bytes is 4, wherein the first way and the second way in the multi-set group associative structure are divided into a first set, and wherein the third way and the fourth way in the multi-set group associative structure are divided into a second set.
4. The method of claim 2, wherein determining hit information at the time of a cache access comprises: Sending a tag access request of the target data to a tag unit; sending a cache access request of target data to an L1D cache; receiving a tag access competition result sent by the tag unit and a cache access competition result sent by the L1D cache; When the label access competition result is successful and the cache access competition result is failed, sending label access confirmation information to the label unit; receiving a label hit result sent by the label unit; and determining hit information during cache access according to the cache access competition result and the tag hit result.
5. The method of claim 3, wherein directly sending the cache access request for the target data to the next level of cache of the current cache further comprises canceling the pipeline follow-up operation.
6. A method as recited in claim 3, further comprising: recording key access information in real time when a tag access request is sent to a tag unit for the first time, wherein the key access information comprises path information; and when the access is repeated, performing cache access according to the key access information.
7. The method of claim 6, wherein recording critical access information in real time comprises recording the critical access information in an instruction queue.
8. The method as recited in claim 7, further comprising: the critical access information in the instruction queue is cleared before the cache line is evicted to the L2 cache.
9. The method as recited in claim 7, further comprising: judging whether the path information is recorded in the instruction queue or not when the cache is accessed repeatedly; If the path information exists, detecting the conflict of the memory bank by using the memory bank with optimized granularity; If the path information does not exist, the storage body conflict detection is carried out by utilizing the storage bodies with the original granularity.
10. The method as recited in claim 9, further comprising: if the path predictor predicts or matches the path information, the memory bank conflict detection is carried out by utilizing the memory bank with optimized granularity according to the predicted or matched path information.
11. The method as recited in claim 4, further comprising: when the cache access request is a loading operation, the hit information is cache access competition success and tag access competition failure, and conflict operation of the loading operation is a filling operation, sub-memory banks which are not occupied by the filling operation in the tag unit are accessed, and the tag memory banks in the tag unit are divided into a plurality of sub-memory banks according to the way information.
12. A cache access control apparatus, comprising: a determining unit for determining hit information at the time of cache access; and the access unit is used for directly sending the cache access request of the target data to the next level cache of the current cache when the hit information is cache access competition failure and the tag is not hit.
13. The apparatus as recited in claim 12, further comprising: A memory bank optimizing unit for performing the following operations: Dividing all cache lines in a cache into a plurality of cache groups according to a multi-path group association structure; Dividing the cache group into a plurality of data blocks according to the designated bit index of the virtual address; splitting a single cache line into a plurality of sub-data segments according to a preset byte number; Grouping the multi-path group connection structures according to the preset path number; and integrating the sub data segments of the cache lines of the corresponding paths according to the grouping of the multi-path group association structure to obtain the storage body with optimized granularity.
14. A computer readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor of a computer device, implements the method of any one of claims 1 to 11.
15. A computer program product comprising a computer program, characterized in that the computer program, when executed by a processor of a computer device, implements the method of any one of claims 1 to 11.

Description

Cache access control method and device Technical Field The present application relates to the field of computer technologies, and in particular, to a method and an apparatus for controlling cache access. Background In the existing superscalar processor architecture, a Load-Store Unit (LSU) optimizes execution efficiency and cache access performance of Load (Load)/Store (Store) instructions through various strategies, and the main technical means include: (1) Cache allocation policy Write Allocation (Write Allocation) when the target address of a store operation misses in the L1D-cache (L1 DATA CACHE), the system loads the corresponding cache line from the lower storage level into the L1D-cache before performing the Write operation. Read Allocation when the target data of the load instruction misses the L1D cache, the system automatically loads the complete cache line containing the data from the lower memory hierarchy and returns the requested data to the processor core. (2) Cache access channel management Single channel time division multiplexing, namely loading, storing operation and filling (Fill) and evicting (Evict) operation of lower level buffer share the same buffer access channel, and the current access authority is determined through an arbitration mechanism. Dynamic prioritization systems typically give higher priority to load instructions to increase execution efficiency, but under certain conditions (e.g., store instruction stacking) can dynamically prioritize to avoid pipeline blocking. (3) Cache addressing and access The Virtual Index Physical Tag (VIPT) technology is that an L1D cache utilizes a virtual address to carry out cache index, and simultaneously, the physical address after TLB/MMU conversion is combined to carry out tag comparison so as to improve the access parallelism. And the system can initiate a lower-level storage access request when the upper-level cache is not hit, so that the waiting time is reduced. (4) Cache organization optimization And the multi-path group connection design adopts a multi-path group connection structure (such as 4 paths) so as to reduce the conflict rate and balance the hardware cost. And (3) dividing a cache memory bank (bank), namely dividing the cache into a plurality of memory banks, supporting multi-instruction parallel access and improving throughput. And the multi-label parallel access supports simultaneous label comparison of a plurality of instructions so as to adapt to the parallel execution requirement of the superscalar processor. However, the handling of cache misses in the above strategy has a response delay problem. When the instruction is aborted due to port contention failure and executed, the instruction needs to wait for rescheduling to perform the complete cache access flow, and then the next-stage cache access request is triggered if a cache miss occurs. This serialized approach results in an extended response time for cache miss situations, increasing overall access latency. Disclosure of Invention The application provides a cache access control method and a cache access control device, which are used for solving the problem of response delay in the processing of cache miss conditions in the prior art. In order to solve the above technical problems, an aspect of the present application provides a cache access control method, which includes: Determining hit information during cache access; And when the hit information is that the cache access competition fails and the tag is not hit, directly sending a cache access request of the target data to the next level cache of the current cache. In a further embodiment of the present application, the cache access control method further includes: optimizing the banks in the cache by: Dividing all cache lines in a cache into a plurality of cache groups according to a multi-path group association structure; Dividing the cache group into a plurality of data blocks according to the designated bit index of the virtual address; splitting a single cache line into a plurality of sub-data segments according to a preset byte number; Grouping the multi-path group connection structures according to the preset path number; and integrating the sub data segments of the cache lines of the corresponding paths according to the grouping of the multi-path group association structure to obtain the storage body with optimized granularity. In a further embodiment of the present application, the predetermined number of bytes is 4, the first way and the second way in the multi-group association structure are divided into the first group, and the third way and the fourth way in the multi-group association structure are divided into the second group. In a further embodiment of the present application, determining hit information during cache access includes: sending a cache access request of the target data to an L1D cache; receiving a tag access competition result sent by the tag unit and a cache access competition r