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CN-121996581-A - Cache miss request processing method and miss state holding register

CN121996581ACN 121996581 ACN121996581 ACN 121996581ACN-121996581-A

Abstract

The embodiment of the invention discloses a cache miss request processing method and a miss state holding register. By combining a cache miss request management mode based on a linked list with a cache miss request management mode based on a class-first-in-first-out, and introducing identification information to represent the entry states of corresponding entries in the linked list so as to select the entries which need to be released currently based on the identification information, the embodiment of the invention can ensure that each cache miss request is processed in sequence according to the arrival sequence as far as possible on the premise that the cache line miss request aiming at the same cache address is processed before the cache block miss request, and simultaneously reduces the area overhead caused by processing the cache miss request.

Inventors

  • TU JIAMING
  • CHEN JIEJUN

Assignees

  • 平头哥(上海)半导体技术有限公司

Dates

Publication Date
20260508
Application Date
20251224

Claims (14)

  1. 1. A method of cache miss request processing, the method comprising: Traversing the stored multiple items according to a storage time sequence by taking the item with the earliest storage time as a traversing starting point to determine a target item, wherein the multiple items are stored in a form of a linked list, the same linked list comprises first items and corresponding second items, the first items are used for representing cache block missing requests, the second items are used for representing cache line missing requests, each first item is provided with corresponding first identification information, the first identification information is used for representing whether each second item corresponding to the first item is released, the target item is the first item to be traversed and meets an execution condition, and the execution condition comprises that the item is the second item or the item is the first item of which the first identification information represents that each second item is released; and generating request execution indication information corresponding to the target entry to indicate execution of the cache miss request corresponding to the target entry.
  2. 2. The method of claim 1, wherein cache miss requests corresponding to entries in the same linked list are for the same cache address; The method further comprises the steps of: Receiving a target cache miss request; determining a target cache address corresponding to the target cache miss request; Determining a corresponding target linked list in a plurality of linked lists according to the target cache address; a target entry is created in the target linked list that characterizes the target cache miss request.
  3. 3. The method of claim 2, wherein after creating a target entry in the target linked list that characterizes the target cache miss request, the method further comprises: And in response to detecting that the target cache miss request is the cache block miss request, updating corresponding first identification information for the target entry.
  4. 4. The method of claim 2, wherein updating the corresponding first identification information for the target entry comprises: In response to detecting that the target item is the first item in the target linked list, determining a second item release condition of the target linked list, and updating corresponding first identification information for the target item according to the second item release condition of the target linked list; And in response to detecting that the target item is not the first item in the target linked list, updating corresponding first identification information for the target item according to the first identification information corresponding to the previous first item in the target linked list.
  5. 5. The method of claim 2, wherein each of the entries further has corresponding second identification information for indicating whether waiting data corresponding to the entry is returned, and wherein the execution condition further includes the second identification information of the entry for indicating that waiting data corresponding to the entry has been returned.
  6. 6. The method of claim 5, wherein after creating a target entry in the target linked list that characterizes the target cache miss request, the method further comprises: And updating the corresponding second identification information for the target item.
  7. 7. The method of claim 6, wherein updating the corresponding second identification information for the target entry comprises: Responding to the detection that the target item is the second item but not the first second item in the target linked list, and updating corresponding second identification information for the target item according to second identification information corresponding to the prior second item in the target linked list; In response to detecting that the target entry is the first entry and is the first entry in the target linked list, querying a corresponding waiting data return condition of the target entry, and updating corresponding second identification information for the target entry according to the corresponding waiting data return condition of the target entry And in response to detecting that the target item is the first item but not the first item in the target linked list, updating corresponding second identification information for the target item according to the second identification information corresponding to the previous first item in the target linked list.
  8. 8. The method of claim 2, wherein each of the entries further has corresponding third identification information for characterizing whether there is a prior atomic operation entry in a linked list in which the entry is located that is not yet completed, the prior atomic operation entry being a prior entry characterizing a cache miss request of an atomic operation type, the execution conditions further comprising third identification information for the entry for characterizing that there is no prior atomic operation entry in the linked list in which the entry is located that is not yet completed, or that there is a prior atomic operation entry in the linked list in which the entry is located that is not yet completed but that is adjacent to the prior atomic operation entry.
  9. 9. The method of claim 8, wherein after creating a target entry in the target linked list that characterizes the target cache miss request, the method further comprises: and updating corresponding third identification information for the target item.
  10. 10. The method of claim 1, wherein the plurality of stored entries are arranged in a storage time order; the step of traversing the stored plurality of items according to the storage time sequence by taking the item with the earliest storage time as the traversal starting point so as to determine the target item comprises the following steps: determining the earliest stored time item in the plurality of items according to a read pointer, wherein the read pointer is configured to point to the earliest stored time item in the plurality of items; And traversing the stored multiple items according to the storage position sequence by taking the item with the earliest storage time as a traversing starting point so as to determine the target item.
  11. 11. A cache miss request processing apparatus, the apparatus comprising: A target item determining unit, configured to traverse, with an item with an earliest storage time as a traversal starting point, a plurality of stored items according to a storage time sequence to determine a target item, where the plurality of items are stored in a form of a linked list, and the same linked list includes a first item and a corresponding second item, where the first item is used to characterize a cache block miss request, the second item is used to characterize a cache line miss request, each first item has corresponding first identification information, the first identification information is used to characterize whether each second item corresponding to the first item is released, the target item is an item that is traversed first to meet an execution condition, and the execution condition includes that the item is the second item or that the item is a first item that the first identification information characterizes that each second item corresponding to the first item is released; and the execution instruction information generation unit is used for generating request execution instruction information corresponding to the target entry so as to instruct execution of the cache miss request corresponding to the target entry.
  12. 12. A miss state holding register disposed in a cache, the miss state holding register comprising: An item memory for storing items; an address comparator for comparing the cache addresses of the entries stored in the entry memory; a controller for performing the method of any one of claims 1-10.
  13. 13. A cache memory, characterized in that, the cache includes: the cache interface is used for receiving a plurality of data access requests; The hit test unit is used for determining whether each data access request hits a corresponding cache or not so as to generate a cache miss request; The miss state holding register of claim 12.
  14. 14. A computer system, the system comprising: the cache of claim 13; and the calculation engine is used for generating a data access request and sending the data access request to the cache.

Description

Cache miss request processing method and miss state holding register Technical Field The present invention relates to the field of computer technology, and more particularly, to a cache miss request processing method and a miss state holding register. Background The miss status holding register (Miss Status Holding Register, MSHR) is a hardware structure for recording and managing cache miss (CACHE MISS) requests that can support concurrent miss handling and data backfilling coordination in non-blocking caches. When processing a cache miss request, an existing miss state holding register generally uses each cache miss request to represent a corresponding entry, stores each entry in a linked list, and then releases each entry included in the linked list in units of the linked list, so as to perform batch processing on the cache miss request represented by each released entry. This type of cache miss request processing method cannot enable each cache miss request to be processed sequentially in the order of arrival as much as possible, while ensuring that a cache line miss request (CACHELINE MISS) for the same cache address is processed before a cache block miss request (sector miss). At the same time, to ensure that a cache line miss request for the same cache address is handled prior to a cache block miss request, existing miss state holding registers need to compare the cache address of the entry with the cache addresses of all entries stored when releasing the entry characterizing the cache block miss request, which also results in a large area overhead. Disclosure of Invention In view of this, the embodiments of the present invention provide a method for processing a cache miss request and a miss status holding register, so that on the premise of ensuring that a cache line miss request for the same cache address is processed before a cache block miss request, each cache miss request is processed sequentially as much as possible according to an arrival order, and meanwhile, area overhead caused by processing the cache miss request is reduced. In a first aspect, an embodiment of the present invention is directed to a method for processing a cache miss request, where the method includes: Traversing the stored multiple items according to a storage time sequence by taking the item with the earliest storage time as a traversing starting point to determine a target item, wherein the multiple items are stored in a form of a linked list, the same linked list comprises first items and corresponding second items, the first items are used for representing cache block missing requests, the second items are used for representing cache line missing requests, each first item is provided with corresponding first identification information, the first identification information is used for representing whether each second item corresponding to the first item is released, the target item is the first item to be traversed and meets an execution condition, and the execution condition comprises that the item is the second item or the item is the first item of which the first identification information represents that each second item is released; and generating request execution indication information corresponding to the target entry to indicate execution of the cache miss request corresponding to the target entry. In a second aspect, embodiments of the present invention are directed to a cache miss request processing apparatus, the apparatus comprising: A target item determining unit, configured to traverse, with an item with an earliest storage time as a traversal starting point, a plurality of stored items according to a storage time sequence to determine a target item, where the plurality of items are stored in a form of a linked list, and the same linked list includes a first item and a corresponding second item, where the first item is used to characterize a cache block miss request, the second item is used to characterize a cache line miss request, each first item has corresponding first identification information, the first identification information is used to characterize whether each second item corresponding to the first item is released, the target item is an item that is traversed first to meet an execution condition, and the execution condition includes that the item is the second item or that the item is a first item that the first identification information characterizes that each second item corresponding to the first item is released; and the execution instruction information generation unit is used for generating request execution instruction information corresponding to the target entry so as to instruct execution of the cache miss request corresponding to the target entry. In a third aspect, embodiments of the present invention are directed to a miss state holding register provided in a cache, the miss state holding register comprising: An item memory for storing items; an address comparator for comparin