CN-121996585-A - Access system, chip and equipment of off-chip nonvolatile memory

CN121996585ACN 121996585 ACN121996585 ACN 121996585ACN-121996585-A

Abstract

The embodiment of the application relates to the technical field of memories and discloses an access system, a chip and equipment of an off-chip nonvolatile memory, wherein the access system comprises at least two processors, a bus matrix and a memory controller; the bus matrix is connected with the Master interface of each processor, the bus matrix is also connected with the storage controller, the storage controller is provided with a corresponding buffer memory for each Master interface, the storage controller is used for connecting the external nonvolatile memory, the buffer memory is used for acquiring information of the corresponding processor which is accessed in advance through the Master interface from the external nonvolatile memory, the processor is used for sending an access request to the bus matrix through the Master interface, and the bus matrix is used for accessing the buffer memory corresponding to the Master interface in the storage controller through the access request. According to the embodiment of the application, the corresponding cache is arranged for each Master interface, so that the reading speed of the off-chip nonvolatile memory is improved, and the running speed of the chip is improved.

Inventors

WANG LI
SHEN YANG

Assignees

加特兰微电子科技(上海)有限公司

Dates

Publication Date: 20260508
Application Date: 20241106

Claims (10)

1. An access system of an off-chip nonvolatile memory is characterized by comprising at least two processors, a bus matrix and a memory controller; The bus matrix is connected with a Master interface of each processor; the bus matrix is also connected with the storage controller, the storage controller is provided with a corresponding buffer memory for each Master interface, the storage controller is used for connecting the external nonvolatile memory, and the buffer memory is used for acquiring the corresponding information pre-accessed by the processor through the Master interface from the external nonvolatile memory in advance; the processor is used for sending an access request to the bus matrix through the Master interface, and the bus matrix is used for accessing the cache corresponding to the Master interface in the storage controller through the access request.
2. The system according to claim 1, wherein the bus matrix is provided with a first bus interface connected in a one-to-one correspondence to each Master interface, the bus matrix is further provided with a plurality of second bus interfaces connected with the memory controller, each processor corresponds to a different second bus interface, the bus matrix obtains an access request obtained by the processor through the Master interface through the first bus interface, and routes the access request to the second bus interface corresponding to the processor to access the cache corresponding to the Master interface of the processor through the corresponding second bus interface; The system also comprises a plurality of conversion modules and reduction modules which are in one-to-one correspondence with the conversion modules, wherein each processor corresponds to different conversion modules and reduction modules; The conversion module is arranged between the Master interface and the first bus interface of the corresponding processor, and the reduction module corresponding to the conversion module is arranged between the second bus interface and the storage controller corresponding to the processor; The conversion module is used for converting an original access address carried in the access request into an intermediate address, and the restoration module corresponding to the conversion module is used for restoring the intermediate address into the original access address.
3. The system for accessing off-chip nonvolatile memory as in claim 2 wherein said Master interface of at least one of said processors is a plurality, said second bus interface being the same as said processors in number and in one-to-one correspondence with said processors; The plurality of Master interfaces of at least one processor are connected to the corresponding plurality of first bus interfaces through the conversion module corresponding to the processor, and the bus matrix is used for routing access requests of the plurality of first bus interfaces to the second bus interfaces corresponding to the processor.
4. The system of claim 3, wherein the plurality of Master interfaces includes at least an instruction bus interface and a data bus interface, wherein the access request of at least one of the processors carries a first type identification, wherein the first type identification indicates that the access request is an instruction request or a data request; the storage controller is configured to determine, according to the first type identifier, the cache that the access request needs to access.
5. The system for accessing off-chip nonvolatile memory of claim 4 wherein the first type identifier is any one of a type signal, a Master ID signal, a User signal.
6. The system according to claim 2, wherein the number of the Master interfaces of at least one processor is a plurality, and the number of the second bus interfaces corresponding to the processor is the same as the number of the Master interfaces and corresponds to each other one by one; The Master interfaces of at least one processor are connected to a corresponding first bus interface through the conversion module corresponding to the Master interface of the processor, the bus matrix is used for respectively routing access requests of the plurality of first bus interfaces to the second bus interface corresponding to the Master interface, and the second bus interface is connected to the storage controller through the reduction module corresponding to the Master interface.
7. The system according to claim 1, wherein the bus matrix is provided with a first bus interface connected in a one-to-one correspondence to each Master interface, and is further provided with a second bus interface connected with the memory controller, the number of the second bus interfaces being one; The storage controller is used for determining the cache which the access request needs to access according to the second type identifier.
8. The system for accessing off-chip nonvolatile memory of claim 7 wherein the second type identifier is any one of a Master ID signal, a User signal.
9. A radar chip comprising an access system for an off-chip nonvolatile memory as claimed in any one of claims 1 to 8.
10. An electronic device comprising the radar chip of claim 9.

Description

Access system, chip and equipment of off-chip nonvolatile memory Technical Field The embodiment of the application relates to the technical field of memories, in particular to an access system, a chip and equipment of an off-chip nonvolatile memory. Background Currently, with the progress of process technology, during system on chip development, a central processing unit (Central Processing Unit, CPU) runs a program and stores the program for reading by means of an off-chip nonvolatile memory (Non Volatile Memory, NVM). However, the speed of dual or multi-core central processing units (Central Processing Unit, CPU) accessing off-chip NVM is still not satisfactory. Disclosure of Invention The embodiment of the application aims to provide an access system, a chip and equipment of an off-chip nonvolatile memory, so that the reading speed of the off-chip nonvolatile memory NVM is improved, and the running speed of the chip is improved. The embodiment of the application provides an access system of an off-chip nonvolatile memory, which comprises at least two processors, a bus matrix and a memory controller, wherein the bus matrix is connected with a Master interface of each processor, the bus matrix is also connected with the memory controller, the memory controller is provided with a corresponding cache for each Master interface, the memory controller is used for connecting the off-chip nonvolatile memory, the cache is used for acquiring information pre-accessed by the corresponding processor through the Master interface from the off-chip nonvolatile memory in advance, the processor is used for sending an access request to the bus matrix through the Master interface, and the bus matrix is used for accessing the cache corresponding to the Master interface in the memory controller through the access request. The embodiment of the application also provides a radar chip, which comprises the access system of the off-chip nonvolatile memory. The embodiment of the application also provides electronic equipment, which comprises the radar chip. The technical scheme provided by the embodiment of the application has at least the following advantages: The memory controller of the embodiment of the application is provided with the corresponding cache for each Master interface so as to solve the technical problem that the prefetching cache is continuously invalid when the single-core system architecture is directly applied to a dual-core or multi-core scene, improve the reading speed of the off-chip nonvolatile memory NVM and improve the running speed of a chip. In addition, the caches corresponding to the Master interfaces are mutually independent, so that the cache is not easily influenced by access requests of other Master interfaces, the stability of prefetching caches is improved, and the running accuracy of a chip is improved. Meanwhile, a plurality of processors can be processed in parallel, so that the running speed of the chip is further improved. Drawings One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated. FIG. 1 is a schematic diagram of an access system for off-chip nonvolatile memory according to an embodiment of the present application; FIG. 2 is a schematic diagram of the operation of a first multiplexer according to one embodiment of the present application; FIG. 3 is a schematic diagram of an access system for off-chip nonvolatile memory according to an embodiment of the present application; FIG. 4 is a schematic diagram of an access system for off-chip nonvolatile memory according to an embodiment of the present application; Fig. 5 is a schematic diagram of the operation of a second multiplexer according to an embodiment of the present application. Detailed Description From the background, the speed of dual-core or multi-core CPUs accessing off-chip nonvolatile memory NVM is still not satisfactory. In the development of the prior art on-chip system, there is usually an on-chip nonvolatile Memory NVM used for storing programs, but for more advanced processes, for example, the on-chip nonvolatile Memory NVM is not present in the process of 22 nm to 16 nm, the CPU can only store the programs for reading by means of the off-chip nonvolatile Memory NVM when running the programs, however, the reading rate of the off-chip nonvolatile Memory NVM is lower, so in order to achieve the same performance as the on-chip NVM, the related art generally adopts a method of loading the data of the off-chip nonvolatile Memory NVM into a Static Random-Access Memory (SRAM) and then running the data on the SRAM, but this method needs to configure the SRAM on-chip, which leads to an increase in cost. In order to avoid the increase of the cost, and simultaneously meet the requirement of directly running o