CN-121996586-A - Memory expansion controller, data processing method and electronic equipment

Abstract

The disclosure provides a memory expansion controller, a data processing method, electronic equipment and a readable storage medium, and relates to the technical field of artificial intelligence such as chips, large models and the like. The memory expansion controller comprises a first protocol control module, a storage control module, a data moving module, a second protocol control module and a CPU (Central processing Unit) expansion memory, wherein the first protocol control module is communicated with the CPU based on a first interconnection protocol, and the second protocol control module is communicated with the AI chip based on a second interconnection protocol. In addition, the disclosure also provides a processing method for writing the AI chip data by the CPU based on the memory expansion controller, a processing method for reading the AI chip data by the CPU, a processing method for writing the AI chip data by the CPU and a processing method for reading the AI chip data by the CPU. The method and the device can improve the flexibility of the type selection of the CPU and the AI chip and the communication bandwidth of the CPU and the AI chip on the basis of not changing the original designs of the CPU and the AI chip.

Inventors

• SONG ZHIYUAN
• LIU YUEJI
• CHI ZHIGANG

Assignees

• 北京百度网讯科技有限公司

Dates

Publication Date

20260508

Application Date

20251209

Claims (20)

1. 1. A memory expansion controller, comprising: The system comprises a first protocol control module, a storage control module, a data moving module, a second protocol control module and a CPU extended memory; The first protocol control module is communicated with the CPU based on the first interconnection protocol, and the second protocol control module is communicated with the AI chip based on the second interconnection protocol.
2. 2. The memory expansion controller of claim 1, wherein the first protocol control module is to: And analyzing a CPU write command sent by the CPU and based on the first interconnection protocol to obtain a data source address of data to be written by the CPU and a first AI chip destination address.
3. 3. The memory expansion controller of claim 2, wherein the data mover module is configured to: And obtaining the local address of the data to be written by the CPU according to the data source address of the data to be written by the CPU, which is obtained by the first protocol control module.
4. 4. The memory expansion controller of claim 3, wherein the storage control module is to: And acquiring the data to be written by the CPU from the CPU expansion memory according to the local address of the data to be written by the CPU, which is obtained by the data moving module.
5. 5. The memory expansion controller of claim 4, wherein the second protocol control module is to: Based on the second interconnection protocol, packaging the data to be written in by the CPU acquired by the storage control module and the first AI chip destination address acquired by the first protocol control module to acquire a first AI chip write command; The first AI chip write command is used for a first AI chip to write the data to be written by the CPU into the first AI chip.
6. 6. The memory expansion controller of claim 1, wherein the first protocol control module is further configured to: And analyzing a CPU read command sent by the CPU and based on the first interconnection protocol to obtain a CPU data read requirement and a second AI chip destination address.
7. 7. The memory expansion controller of claim 6, wherein the second protocol control module is further configured to: Based on the second interconnection protocol, packaging the CPU data reading requirement obtained by the first protocol control module and the second AI chip destination address to obtain a second AI chip reading command; the second AI chip reading command is used for the second AI chip to acquire a CPU data reading result; And analyzing a CPU data reading result returned by the second AI chip and based on the second interconnection protocol to obtain CPU data to be read corresponding to the CPU data reading requirement.
8. 8. The memory expansion controller of claim 7, wherein the storage control module is further to: And writing the data to be read of the CPU, which is obtained by the second protocol control module, into the CPU extended memory so as to be used for reading the data to be read of the CPU by the CPU through the CPU extended memory.
9. 9. The memory expansion controller of claim 1, wherein the second protocol control module is further configured to: And analyzing a target AI chip write command sent by the target AI chip and based on the second interconnection protocol to obtain data to be written by the AI chip and a data destination address of the data to be written by the AI chip.
10. 10. The memory expansion controller of claim 9, wherein the data mover module is further configured to: And obtaining the local address of the data to be written in the AI chip according to the data destination address of the data to be written in the AI chip obtained by the second protocol control module.
11. 11. The memory expansion controller of claim 10, wherein the storage control module is further to: And writing the data to be written into the CPU expansion memory by the AI chip obtained by the second protocol control module according to the local address of the data to be written into the AI chip obtained by the data moving module.
12. 12. The memory expansion controller of claim 1, wherein the second protocol control module is further configured to: And analyzing a target AI chip read command based on the second interconnection protocol sent by the target AI chip to obtain a data source address of data to be read of the AI chip.
13. 13. The memory expansion controller of claim 12, wherein the data mover module is further configured to: And obtaining the local address of the data to be read of the AI chip according to the data source address of the data to be read of the AI chip obtained by the second protocol control module.
14. 14. The memory expansion controller of claim 13, wherein the storage control module is further to: And acquiring the data to be read of the AI chip from the CPU expansion memory according to the local address of the data to be read of the AI chip obtained by the data moving module.
15. 15. The memory expansion controller of claim 14, wherein the second protocol control module is further configured to: based on the second interconnection protocol, the AI chip data to be read acquired by the storage control module is packaged, and an AI chip data reading result is obtained; The AI chip data reading result is used for being sent to the target AI chip so that the target AI chip can read the AI data to be read according to the AI chip data reading result.
16. 16. A data processing method based on a memory expansion controller according to any of claims 1-15, comprising: After receiving a CPU write command based on a first interconnection protocol sent by a CPU, a memory expansion controller analyzes the CPU write command by using a first protocol control module to obtain a data source address of data to be written by the CPU and a first AI chip destination address; A data moving module is used for obtaining a local address of the data to be written by the CPU according to the data source address of the data to be written by the CPU; The method comprises the steps that a storage control module is used for acquiring data to be written by a CPU from a CPU expansion memory according to a local address of the data to be written by the CPU; using a second protocol control module, and packaging the data to be written in by the CPU and the destination address of the first AI chip based on a second interconnection protocol to obtain a first AI chip writing command; And sending the first AI chip write command to a first AI chip so that the first AI chip writes the data to be written by the CPU into a video memory.
17. 17. A data processing method based on a memory expansion controller according to any of claims 1-15, comprising: after receiving a CPU read command based on a first interconnection protocol sent by a CPU, a memory expansion controller analyzes the CPU read command by using a first protocol control module to obtain a CPU data read requirement and a second AI chip destination address; using a second protocol control module, and packaging the CPU data reading requirement and a second AI chip destination address based on a second interconnection protocol to obtain a second AI chip reading command; After the second AI chip reading command is sent to a second AI chip, analyzing a CPU data reading result returned by the second AI chip and based on the second interconnection protocol by using the second protocol control module to obtain data to be read by the CPU; And writing the data to be read by the CPU into a CPU extended memory by using a storage controller module, so that the CPU can read the data to be read by the CPU through the CPU extended memory.
18. 18. A data processing method based on a memory expansion controller according to any of claims 1-15, comprising: After receiving a target AI chip write command based on a second interconnection protocol sent by a target AI chip, the memory expansion controller uses a second protocol control module to analyze the target AI chip write command to obtain data to be written by the AI chip and a data destination address of the data to be written by the AI chip; a data moving module is used for obtaining a local address of the data to be written in the AI chip according to the data destination address data of the data to be written in the AI chip; And using a storage control module to write the data to be written into the CPU expansion memory according to the local address of the data to be written into the AI chip.
19. 19. A data processing method based on a memory expansion controller according to any of claims 1-15, comprising: after receiving a target AI chip read command based on a second interconnection protocol sent by a target AI chip, the memory expansion controller uses a second protocol control module to analyze the target AI chip read command and acquire a data source address of data to be read of the AI chip; A data moving module is used for obtaining a local address of the data to be read of the AI chip according to the data source address of the data to be read of the AI chip; acquiring the data to be read of the AI chip from the CPU extended memory according to the local address of the data to be read of the AI chip by using a storage control module; Using the second protocol control module to package the data to be read of the AI chip into an AI chip data reading result based on the second interconnection protocol; And sending the AI chip data reading result to the target AI chip so as to be used for the target AI chip to read the data to be read of the AI chip according to the AI chip data reading result.
20. 20. An AI server system comprising a CPU, at least one AI chip, and the memory expansion controller of any of claims 1-15.

Description

Memory expansion controller, data processing method and electronic equipment Technical Field The disclosure relates to the field of computer technology, and in particular to the technical field of artificial intelligence such as chips, large models and the like. A memory expansion controller, a data processing method, an electronic device and a readable storage medium are provided. Background In an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) server, a central processing unit (Central Processing Unit, CPU) is good at handling complex logic control and serial computing tasks, an AI chip is good at handling massive parallel computing tasks, and in order to achieve efficient parallel computing, high-speed data exchange is required between the CPU and the AI chip to reduce delay of data transmission. In the prior art, if the original design of the CPU and the AI chip is not changed, the communication between the CPU and the AI chip is usually performed by using a PCIe interconnection protocol, but the communication bandwidth is low when the communication is performed by using the PCIe interconnection protocol, and the delay in data transmission cannot be effectively reduced. Therefore, how to improve the communication bandwidth between the CPU and the AI chip without changing the original designs of the CPU and the AI chip is a technical problem to be solved. Disclosure of Invention According to a first aspect of the disclosure, a memory expansion controller is provided, which comprises a first protocol control module, a storage control module, a data moving module, a second protocol control module and a CPU (central processing unit) for expanding a memory, wherein the first protocol control module is communicated with the CPU based on a first interconnection protocol, and the second protocol control module is communicated with an AI (analog to digital) chip based on a second interconnection protocol. According to a second aspect of the present disclosure, a data processing method is provided, which includes that after a memory expansion controller receives a CPU write command based on a first interconnection protocol sent by a CPU, the CPU write command is resolved by using a first protocol control module to obtain a data source address of data to be written by the CPU and a first AI chip destination address, a data moving module is used to obtain a local address of the data to be written by the CPU according to the data source address of the data to be written by the CPU, a memory control module is used to obtain the data to be written by the CPU from a CPU expansion memory according to the local address of the data to be written by the CPU, a second protocol control module is used to package the data to be written by the CPU and the first AI chip destination address based on a second interconnection protocol to obtain a first AI chip write command, and the first AI chip write command is sent to a first AI chip to enable the first AI chip to write the data to be written by the CPU into a video memory. According to a third aspect of the disclosure, a data processing method is provided, which includes that after a memory expansion controller receives a CPU read command based on a first interconnection protocol sent by a CPU, the CPU read command is analyzed by a first protocol control module to obtain a CPU data read requirement and a second AI chip destination address, the CPU data read requirement and the second AI chip destination address are packaged by the second protocol control module based on the second interconnection protocol to obtain a second AI chip read command, after the second AI chip read command is sent to a second AI chip, a CPU data read result based on the second interconnection protocol returned by the second AI chip is analyzed by the second protocol control module to obtain CPU data to be read, and the CPU data to be read is written into a CPU expansion memory by a storage controller module to be used for the CPU to read the CPU data to be read through the CPU expansion memory. According to a fourth aspect of the present disclosure, a data processing method is provided, including that after a memory expansion controller receives a target AI chip write command based on a second interconnection protocol sent by a target AI chip, the target AI chip write command is parsed by using a second protocol control module to obtain AI chip data to be written and a data destination address of the AI chip data to be written, a data moving module is used to obtain a local address of the AI chip data to be written according to the AI chip data destination address data, and a memory control module is used to write the AI chip data to be written into a CPU expansion memory according to the AI chip data to be written. According to a fifth aspect of the present disclosure, a data processing method is provided, including a memory expansion controller analyzing a target AI chip read command based on