CN-121996587-A - Flash memory controller, solid state disk controller and electronic equipment

CN121996587ACN 121996587 ACN121996587 ACN 121996587ACN-121996587-A

Abstract

The application discloses a flash memory controller, a solid state disk controller and electronic equipment, and belongs to the technical field of storage. The flash memory controller comprises a queue manager and a flash memory processor, wherein the queue manager is coupled with the flash memory processor, the queue manager is used for managing a command queue aiming at a flash memory grain, the command queue comprises flash memory operation commands to be executed, the flash memory operation commands comprise at least one of cache read commands and cache programming commands, and the flash memory processor is used for executing the flash memory operation commands.

Inventors

HU MIN
YANG ZHIHAO
ZHANG TONG
XIAO ZIHUA
WANG YING

Assignees

联芸科技(杭州)股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260119

Claims (10)

1. The flash memory controller is characterized by comprising a queue manager and a flash memory processor, wherein the queue manager is coupled with the flash memory processor; The queue manager is configured to manage a command queue for a flash memory die, where the command queue includes a flash memory operation command to be executed, and the flash memory operation command includes at least one of a cache read command and a cache program command; the flash memory processor is used for executing the flash memory operation command.
2. The flash controller of claim 1, wherein the flash processor comprises a scheduling unit, an execution unit, and a flash state recording unit; The scheduling unit is used for acquiring a first command from the command queue; the flash memory state recording unit is used for storing the register state of the flash memory grain; The execution unit is configured to query a register state corresponding to the first command from the flash memory state recording unit, and execute the first command when the register state corresponding to the first command meets a first condition.
3. The flash memory controller of claim 2, wherein, The queue manager is further configured to submit a second command to the scheduling unit if it is detected that the second command exists in the command queue; the execution unit is further configured to save a context of the first command, let the first command enter a sleep state, exit execution of the first command, and execute the second command.
4. The flash memory controller of claim 3, wherein the execution unit is further configured to query the flash memory state recording unit for a register state of the second command, and to actively exit execution of the second command and resume execution of the first command if the register state of the second command satisfies a second condition.
5. The flash memory controller of claim 4, wherein the first command is a normal read command and the second command is a cache read command; The execution unit is further configured to determine whether a page address of the second command is consecutive with a page address of the first command, execute a sequential cache read command if the page address of the second command is consecutive with the page address of the first command, and execute a random cache read command if the page address of the second command is not consecutive with the page address of the first command.
6. The flash controller of claim 4, wherein the execution unit is further to: Acquiring a command state of a target command, wherein the target command comprises at least one of the first command and the second command; updating a register state corresponding to the target command in the flash memory state recording unit based on the command state of the target command; And under the condition that the target command comprises the first command, after the first command resumes execution, acquiring a register state corresponding to the first command from the flash memory state recording unit.
7. The flash memory controller of claim 6, wherein the first command is a normal program command and the second command is a cache program command, the command status including program success or program failure; the execution unit is further configured to replace a program confirm command with a cache program confirm command if it is detected that a second command exists in the command queue.
8. The flash memory controller of any one of claims 1-7, wherein the queue manager is further configured to determine a scheduling decision based on a queue status of the command queue and whether each command in the command queue allows execution of a specified command, the specified command including at least one of the cache read command and a cache program command; the queue state comprises an empty queue or a non-empty queue, the command queue comprises a cache operation sequence, and the scheduling decision comprises any one of starting the cache operation sequence, maintaining the cache operation sequence and terminating the cache operation sequence.
9. A solid state disk controller comprising a central processor and a flash memory controller according to any one of claims 1-8.
10. An electronic device comprising the solid state disk controller of claim 9.

Description

Flash memory controller, solid state disk controller and electronic equipment Technical Field The application belongs to the technical field of storage, and particularly relates to a flash memory controller, a solid state disk controller and electronic equipment. Background Cache read (CACHE READ)/Cache Program (Cache Program) commands are efficient commands provided for flash memory, aiming to hide the latency of command and address loading by pipelining, thereby improving data bandwidth. However, the "prefetch" and "delayed acknowledge" nature of the Cache read (CACHE READ)/Cache Program (Cache Program) commands breaks the simple paradigm of traditional "send command-wait for completion-process results" introducing cross-dependencies between operations. These cross operations are managed and scheduled in software entirely by Firmware (FW) in the related art, which breaks down a cache command into discrete, strongly dependent small granularity units and takes care of synchronization between them. However, this manner of completing the cache command by the firmware in the related art may lead to a complex condition judgment in the firmware code, which is difficult to ensure that the firmware code is correctly synchronized under all boundary conditions, and there is a reliability risk. Disclosure of Invention The embodiment of the application provides a flash memory controller, a solid state disk controller and electronic equipment, which can solve the problem that the mode of completing a cache command by firmware in the related art has reliability risk. In a first aspect, an embodiment of the present application provides a flash memory controller, including a queue manager and a flash memory processor, wherein the queue manager is coupled to the flash memory processor; The queue manager is configured to manage a command queue for a flash memory die, where the command queue includes a flash memory operation command to be executed, and the flash memory operation command includes at least one of a cache read command and a cache program command; the flash memory processor is used for executing the flash memory operation command. In a second aspect, an embodiment of the present application provides a solid state hard disk controller, including a flash memory controller as described in the first aspect. In a third aspect, an embodiment of the present application provides an electronic device, including a central processing unit and a solid state disk controller according to the second aspect. In the embodiment of the application, the command queue for the flash memory grain is managed by the queue manager in the flash memory controller, and at least one of the cache read command and the cache program command is executed by the flash memory processor in the flash memory controller, so that the cache command can be realized by the hardware of the flash memory controller. Drawings FIG. 1 is a schematic diagram of an SSD controller; FIG. 2 is a schematic diagram of a flash memory controller according to an embodiment of the present application; FIG. 3 is a schematic diagram of another hard disk controller according to an embodiment of the present application; FIG. 4 is a schematic diagram of a cache read automation workflow provided by an embodiment of the present application; FIG. 5-1 is a schematic diagram of a process by which a queue manager submits commands to a dispatch unit; fig. 5-2 is a schematic diagram of an implementation of a cache read command. FIG. 6 is a schematic diagram of a cache programming automation workflow provided by an embodiment of the present application; FIG. 7-1 is a schematic diagram of a process by which a queue manager submits commands to a dispatch unit; FIG. 7-2 is a schematic diagram of an implementation of a cache program command; FIG. 8 is a block diagram of an SSD controller according to an embodiment of the present application; Fig. 9 is a block diagram of an electronic device according to an embodiment of the present application. Detailed Description The technical solutions of the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application. The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects iden