CN-121996588-A - Optimization method, system and equipment for multi-period initialization standard time sequence calibration flow

CN121996588ACN 121996588 ACN121996588 ACN 121996588ACN-121996588-A

Abstract

The application relates to an optimization method, a system and equipment for a multi-period initialization standard time sequence calibration flow. The method comprises the steps of obtaining the initialization standard time sequence calibration flow result of each DDR3 particle. Dividing the results of the initialization standard time sequence calibration flow into two groups according to the sequence numbers of particles, and respectively calculating the slope of each group by adopting a least square method. Judging whether particles to be corrected exist according to the slope, if so, automatically updating the register configuration of the corresponding particles so as to align the DQS rising edge with the correct CLK rising edge. The method can remarkably reduce the occupation of system computing resources and development and maintenance cost, and achieves full-automatic and high-reliability multi-period initialization standard time sequence calibration flow correction.

Inventors

CHEN HUI
WU XIANGDI
HUANG JIAN
GONG GUOHUI

Assignees

湖南长城银河科技有限公司

Dates

Publication Date: 20260508
Application Date: 20260211

Claims (9)

1. An optimization method of a multi-period initialization standard time sequence calibration flow is characterized by comprising the following steps: acquiring an initialization standard time sequence calibration flow result of each DDR3 particle; Dividing the initialization standard time sequence calibration flow result into two groups according to particle sequence numbers, and respectively calculating the slope of each group by adopting a least square method; Judging whether particles needing to be corrected exist according to the slope, if so, automatically updating the register configuration of the corresponding particles so as to align the DQS rising edge with the correct CLK rising edge.
2. The method of claim 1, wherein dividing the initialization standard timing calibration procedure result into two groups by particle number, comprises: Dividing initialization standard time sequence calibration flow results corresponding to the particle serial numbers of 0,1,2 and 3 into a first group; And dividing the results of the initialization standard time sequence calibration flow corresponding to the particle serial numbers 4, 5, 6 and 7 into a second group.
3. The method of claim 1, wherein calculating the slope of each packet using the least squares method, respectively, comprises: The slope of the data in each packet is calculated by a least square method: Wherein, the Is the slope of the slope, For the sequence number of the data in the packet, Is a natural number label, and is characterized by that, As an average of the sequence numbers in the packet, For data sequence numbers in packets In response to the data set, As an average value of the data in the packet, Is the total number of labels.
4. A method according to any one of claims 1 to 3, wherein determining whether there are particles to be corrected based on the slope comprises: if the first group slope is greater than 0 and the second group slope is greater than 0, determining that correction is not needed; If the first group of slopes is smaller than 0, judging that the particle numbers 0 and 1 need to be corrected, or that the particle number 0 needs to be corrected, or that the particle number 1 needs to be corrected; if the second group slope is less than 0, it is determined that particle numbers 6 and 7 need to be corrected, or that particle number 6 needs to be corrected, or that particle number 7 needs to be corrected.
5. The method of claim 4, further comprising, after determining that particle numbers 0 and 1 require correction, or that particle number 0 requires correction, or that particle number 1 requires correction; Calculating a first absolute value of a difference value between an initialization standard time sequence calibration flow result corresponding to a particle sequence number 2 and a particle sequence number 0, and a second absolute value of a difference value between an initialization standard time sequence calibration flow result corresponding to a particle sequence number 2 and a particle sequence number 1, and taking the maximum value of the first absolute value and the second absolute value as a reference value; and comparing the initialization standard time sequence calibration flow results corresponding to the particle serial number 0 and the particle serial number 1 according to the reference value, and determining the specific particle to be corrected.
6. The method of claim 5, wherein if there are particles to be corrected, automatically updating the register configuration of the corresponding particles to align the DQS rising edge with the correct CLK rising edge, comprising; If the particle number is 0 and needs to be corrected, the register configuration of the corresponding particle is automatically updated, if the particle number is 1 and needs to be corrected, the corresponding initialization standard time sequence calibration flow result is reduced by one period value, if the particle number is 6 and needs to be corrected, the corresponding initialization standard time sequence calibration flow result is increased by one period value, and if the particle number is 7 and needs to be corrected, the corresponding initialization standard time sequence calibration flow result is increased by one period value.
7. An optimization system for a multi-cycle initialization standard timing calibration procedure, the system comprising: The flow result acquisition module is used for acquiring the initialization standard time sequence calibration flow result of each DDR3 particle; The slope calculation module is used for dividing the initialization standard time sequence calibration flow result into two groups according to particle sequence numbers, and calculating the slope of each group by adopting a least square method; And the calibration module is used for judging whether particles needing to be corrected exist according to the slope, and if the particles needing to be corrected exist, automatically updating the register configuration of the corresponding particles so as to align the DQS rising edge with the correct CLK rising edge.
8. The system of claim 7, wherein the slope calculation module is further configured to calculate the slope of the data in each packet using a least squares method, respectively: Wherein, the Is the slope of the slope, For the sequence number of the data in the packet, Is a natural number label, and is characterized by that, As an average of the sequence numbers in the packet, For data sequence numbers in packets In response to the data set, As an average value of the data in the packet, Is the total number of labels.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1 to 7 when the computer program is executed.

Description

Optimization method, system and equipment for multi-period initialization standard time sequence calibration flow Technical Field The application relates to the technical field of DDR3 driving software algorithm development, in particular to an optimization method, system and equipment for a multi-period initialization standard time sequence calibration flow. Background In the prior art, when the wiring delay between DQS and CLK in DDR3 system is larger than one clock cycle or DQS rising edge falls into CLK to establish a hold time window, the problems of dependence on manual intervention, poor system adaptability, high realization cost and the like of calibration results are commonly existed, and the reliability and application flexibility of a high-speed memory interface are restricted. Specifically, according to the JEDEC JESD79-3F protocol, WRITE LEVELING aims to align the DQS rising edge with the CLK rising edge under specified write timing parameters (CWL) to meet the timing requirements of tDQSS, tDSS, and tDSH. In DDR3 systems that actually employ fly-by topologies, there may be multi-cycle delays or critical timing offsets between CLK and DQS received by each particle due to differences in the trace lengths of the clock, command/address signals and the data bus (DQS/DQ). The conventional WRITE LEVELING algorithm achieves alignment by DQS delay scanning and sampling the CLK feedback value, but its correction range is typically limited to one cycle. When the delay exceeds one cycle or the DQS edge is in the CLK setup hold window, the algorithm may erroneously align DQS with the adjacent cycle CLK edge, resulting in failure of subsequent read and write operations. To cope with the multi-period delay problem, two types of schemes are mainly proposed in the prior art, but obvious limitations exist. The first category of schemes is represented by U.S. Pat. No. 10,297,310 B2, which detects cycle skew by writing a specific data pattern at successive addresses in conjunction with DQS pulse gating. The scheme can realize multi-period identification, but the effectiveness of the scheme depends on the absolute correctness of read-write operation, and the scheme is judged to be invalid if the read error occurs, and meanwhile, the scheme requires that a configurable DQS (DQS) gating circuit (such as a special PLL) is arranged in the DDR controller, so that the complexity of hardware design is increased, and the chip of the streamed chip cannot be updated in the later period. The second scheme takes the technical document of the TI company DDR3 Design Requirements for KeyStone Device as an example, and avoids the multi-period problem from the physical design by applying strict time sequence constraint to the PCB wiring (for example, the delay difference between DQS and CLK is required to be less than one period). The method simplifies the software flow, but greatly limits the freedom degree of layout and wiring of the circuit board, improves the hardware design difficulty and cost, and is not beneficial to popularization and use of chips in diversified hardware environments. In addition, existing software flows often lack automatic analysis and correction mechanisms for WRITE LEVELING results for DDR3 controllers that support latency adjustment capabilities of more than 1 cycle. When multi-period alignment errors occur, the developer still needs to manually read each particle calibration result, identify abnormal particles and manually calculate a register correction value. The process is time-consuming, labor-consuming, easy to make mistakes, and can not adapt to the differences of different customer PCB designs, so that each hardware change needs to be debugged again manually, and the project development and maintenance cost is increased. Therefore, there is a strong need in the art for an all-software solution capable of automatically identifying and correcting multi-cycle WRITE LEVELING anomalies that does not rely on specific hardware functions, does not impose additional constraints on the PCB design, and can adaptively accomplish timing calibration without human intervention, thereby improving system reliability, compatibility, and development efficiency. Disclosure of Invention Based on this, it is necessary to provide an optimization method, system and device for multi-cycle initialization standard time sequence calibration procedure, which can reduce the system computing resource occupation and development and maintenance costs. An optimization method of a multi-cycle initialization standard timing calibration procedure, the method comprising: and obtaining the initialization standard time sequence calibration flow result of each DDR3 particle. Dividing the results of the initialization standard time sequence calibration flow into two groups according to the sequence numbers of particles, and respectively calculating the slope of each group by adopting a least square method. Judging whether particles to