CN-121996596-A - Receiver circuit with parallel trigger circuitry

Abstract

Embodiments of the application relate to a receiver circuit with parallel trigger circuitry. For example, the receiver circuit [100] comprises first trigger circuitry [102] configured with a first trigger level for a low-to-high transition of an input signal applied to an input node [101] of the receiver circuit [100], and second trigger circuitry [104] arranged at least partially in parallel with the first trigger circuitry [102] and configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different from the first trigger level. Respective inputs of the first and second trigger circuitry are coupled to the input node [101] of the receiver circuit [100], and respective outputs of the first and second trigger circuitry [102] and [104] are coupled to an output node of the receiver circuit [100 ].

Inventors

• S. Shetty
• R. Yadav

Assignees

• 德州仪器公司

Dates

Publication Date

20260508

Application Date

20251022

Priority Date

20241106

Claims (20)

1. 1. A receiver circuit, comprising: a first trigger circuitry configured with a first trigger level for a low to high transition of an input signal applied to an input node of the receiver circuit, and Second trigger circuitry arranged at least partially in parallel with the first trigger circuitry and configured with a second trigger level for a high to low transition of the input signal, the second trigger level being different from the first trigger level; Wherein respective inputs of the first and second trigger circuitry are coupled to the input node of the receiver circuit and respective outputs of the first and second trigger circuitry are coupled to an output node of the receiver circuit.
2. 2. The receiver circuit of claim 1, further comprising control circuitry configured to enable the first trigger circuitry and the second trigger circuitry simultaneously in response to an applied control signal.
3. 3. The receiver circuit of claim 1, wherein the first trigger circuitry is configured to drive the output node of the receiver circuit to one of a logic high level and a logic low level in response to the low-to-high transition of the input signal, and the second trigger circuitry is configured to drive the output node of the receiver circuit to the other of the logic high level and the logic low level in response to the high-to-low transition of the input signal.
4. 4. The receiver circuit of claim 1, wherein the first and second trigger circuitry comprise respective first and second inverters, each of the first and second inverters having an input coupled to the input node of the receiver circuit and an output coupled to the output node of the receiver circuit.
5. 5. The receiver circuit of claim 4, wherein each of the first inverter and the second inverter comprises a first P-type field effect transistor and a first N-type field effect transistor, the field effect transistors each having a gate terminal, a source terminal, and a drain terminal, the gate terminal coupled to the input node of the receiver circuit, the source terminal of the first P-type field effect transistor coupled to an upper power supply terminal of the receiver circuit, the drain terminal of the first P-type field effect transistor coupled to the drain terminal of the first N-type field effect transistor, and the source terminal of the first N-type field effect transistor coupled to a lower power supply terminal of the receiver circuit.
6. 6. The receiver circuit of claim 5, wherein the first trigger circuitry further comprises an additional P-type field effect transistor having a gate terminal coupled to the first P-type field effect transistor and the respective drain terminal of the first N-type field effect transistor of the first inverter, a source terminal coupled to the upper power supply terminal, and a drain terminal coupled to the output node of the receiver circuit.
7. 7. The receiver circuit of claim 5, wherein the second trigger circuitry further comprises an additional N-type field effect transistor having a gate terminal coupled to the first P-type field effect transistor and the respective drain terminal of the first N-type field effect transistor of the second inverter, a source terminal coupled to the lower power supply terminal, and a drain terminal coupled to the output node of the receiver circuit.
8. 8. The receiver circuit of claim 4, wherein channel sizes of respective P-type field effect transistors and N-type field effect transistors of the first inverter are configured at a first ratio that at least partially sets the first trigger level, and channel sizes of respective P-type field effect transistors and N-type field effect transistors of the second inverter are configured at a second ratio that at least partially sets the second trigger level, the second ratio being different from the first ratio.
9. 9. The receiver circuit of claim 8, wherein the first ratio is between approximately 4:1 and approximately 6:1, and the second ratio is between approximately 0.8:1 and approximately 1.2:1.
10. 10. The receiver circuit of claim 1, wherein the first and second trigger circuitry comprise respective first and second schmitt trigger circuits, wherein the respective first and second trigger levels are configured based at least in part on utilization of different channel sizes for respective corresponding field effect transistors in the first and second schmitt trigger circuits.
11. 11. The receiver circuit of claim 1, further comprising a level shifter coupled between the outputs of the respective first and second trigger circuitry and the output node of the receiver circuit.
12. 12. The receiver circuit of claim 1, further comprising a latch circuit coupled between the outputs of the respective first and second trigger circuitry and the output node of the receiver circuit.
13. 13. The receiver circuit of claim 12, wherein the latch circuit comprises a series arrangement of a plurality of inverters, wherein an input of a first one of the plurality of inverters is coupled to the outputs of the respective first and second trigger circuitry, an output of the first one of the plurality of inverters is coupled to an input of another one of the plurality of inverters, and an output of the another one of the plurality of inverters is coupled to the outputs of the first and second trigger circuitry.
14. 14. The receiver circuit of claim 12, wherein an output of the latch circuit is coupled to an input of a level shifter circuit and an output of the level shifter circuit is coupled to the output node of the receiver circuit.
15. 15. An integrated circuit, comprising: A plurality of receiver circuits, and Additional circuitry coupled to the plurality of receiver circuits; wherein at least one of the receiver circuits comprises: a first trigger circuitry configured with a first trigger level for a low to high transition of an input signal applied to an input node of the receiver circuit, and Second trigger circuitry arranged at least partially in parallel with the first trigger circuitry and configured with a second trigger level for a high to low transition of the input signal, the second trigger level being different from the first trigger level; Wherein respective inputs of the first and second trigger circuitry are coupled to the input node of the receiver circuit and respective outputs of the first and second trigger circuitry are coupled to an output node of the receiver circuit.
16. 16. The integrated circuit of claim 15, wherein the first trigger circuitry is configured to drive the output node of the corresponding receiver circuit to one of a logic high level and a logic low level in response to the low-to-high transition of the input signal, and the second trigger circuitry is configured to drive the output node of the corresponding receiver circuit to the other of the logic high level and the logic low level in response to the high-to-low transition of the input signal.
17. 17. The integrated circuit of claim 15, wherein the first and second trigger circuitry comprise respective first and second inverters, each of the first and second inverters having an input coupled to the input node of the corresponding receiver circuit and an output coupled to the output node of the corresponding receiver circuit.
18. 18. The integrated circuit of claim 17, wherein channel sizes of respective P-type field effect transistors and N-type field effect transistors of the first inverter are configured at a first ratio that at least partially sets the first trigger level, and channel sizes of respective P-type field effect transistors and N-type field effect transistors of the second inverter are configured at a second ratio that at least partially sets the second trigger level, the second ratio being different from the first ratio.
19. 19. A method of manufacturing an integrated circuit, comprising: Forming a plurality of receiver circuits, and Forming additional circuitry; Wherein the receiver circuit is coupled to the additional circuitry, and Wherein forming each of one or more of the receiver circuits comprises: forming first trigger circuitry configured with a first trigger level for a low-to-high transition of an input signal applied to an input node of the receiver circuit; forming second trigger circuitry arranged at least partially in parallel with the first trigger circuitry and configured with a second trigger level for a high to low transition of the input signal, the second trigger level being different from the first trigger level; Wherein respective inputs of the first and second trigger circuitry are coupled to the input node of the receiver circuit and respective outputs of the first and second trigger circuitry are coupled to an output node of the receiver circuit.
20. 20. The method of claim 19, wherein forming the first trigger circuitry comprises forming respective P-type field effect transistors and N-type field effect transistors of a first inverter of the first trigger circuitry, the respective P-type field effect transistors and N-type field effect transistors having channel sizes at a first ratio that at least partially sets the first trigger level, and forming the second trigger circuitry comprises forming respective P-type field effect transistors and N-type field effect transistors of a second inverter of the second trigger circuitry, the respective P-type field effect transistors and N-type field effect transistors having channel sizes at a second ratio that at least partially sets the second trigger level, the second ratio different from the first ratio.

Description

Receiver circuit with parallel trigger circuitry Technical Field The present disclosure relates to the field of electronic circuits and systems, and more particularly, but not exclusively, to receiver circuits. Background Receiver circuitry is illustratively used as part of input/output (I/O) circuitry in integrated circuits, as well as in many other applications. In some applications, such receiver circuits receive input signals from other integrated circuits and/or from other external components of the electronic system. Disclosure of Invention The present disclosure describes receiver circuits with trigger circuitry in parallel, as well as integrated circuits containing such receiver circuits, and related methods. This summary is not an extensive overview of the disclosure. Indeed, the purpose of this summary is to present some examples of the disclosure in a simplified form as a prelude to the more detailed description that is presented later. In some examples, a receiver circuit includes first trigger circuitry configured with a first trigger level for a low-to-high transition of an input signal applied to an input node of the receiver circuit, and second trigger circuitry arranged at least partially in parallel with the first trigger circuitry and configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different from the first trigger level. Respective inputs of the first and second trigger circuitry are coupled to an input node of the receiver circuit, and respective outputs of the first and second trigger circuitry are coupled to an output node of the receiver circuit. In some other examples, an integrated circuit includes a plurality of receiver circuits and additional circuitry coupled to the plurality of receiver circuits. At least one of the receiver circuits comprises first trigger circuitry configured with a first trigger level for a low to high transition of an input signal applied to an input node of the receiver circuit, and second trigger circuitry arranged at least partly in parallel with the first trigger circuitry and configured with a second trigger level for a high to low transition of the input signal, the second trigger level being different from the first trigger level. Respective inputs of the first and second trigger circuitry are coupled to an input node of the receiver circuit, and respective outputs of the first and second trigger circuitry are coupled to an output node of the receiver circuit. In some additional examples, a method of manufacturing an integrated circuit includes forming a plurality of receiver circuits, and forming additional circuitry, wherein the receiver circuits are coupled to the additional circuitry, and wherein forming one or more of the receiver circuits each includes forming first trigger circuitry configured with a first trigger level for a low-to-high transition of an input signal applied to an input node of the receiver circuits, and forming second trigger circuitry arranged at least partially in parallel with the first trigger circuitry and configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different from the first trigger level. Respective inputs of the first and second trigger circuitry are coupled to an input node of the receiver circuit, and respective outputs of the first and second trigger circuitry are coupled to an output node of the receiver circuit. Drawings Fig. 1 illustrates a receiver circuit with trigger circuitry in parallel according to an example of the present disclosure; FIG. 2 is a block diagram of an integrated circuit including multiple receiver circuits and additional circuitry according to an example of the present disclosure; Fig. 3 is a schematic diagram of an implementation of the receiver circuit of fig. 1, according to an example of the present disclosure; fig. 4 and 5 are timing diagrams illustrating the operation of a receiver circuit with trigger circuitry in parallel according to an example of the present disclosure; fig. 6 illustrates another receiver circuit with parallel trigger circuitry in which schmitt trigger circuitry is utilized in accordance with an example of the present disclosure; FIG. 7 is a flow chart illustrating a method of operating a receiver circuit according to an example of the present disclosure, and Fig. 8 is a flow chart illustrating a method of manufacturing an integrated circuit including a plurality of receiver circuits according to an example of the present disclosure. Detailed Description The present disclosure is described with reference to the accompanying drawings. The components in the figures are not drawn to scale. Emphasis instead being placed upon clearly illustrating the general features and principles of the present disclosure. Numerous specific details and relationships are set forth with reference to examples of drawings to provide an understa