Search

CN-121996598-A - Multi-mode heterogeneous computing processing system

CN121996598ACN 121996598 ACN121996598 ACN 121996598ACN-121996598-A

Abstract

The invention discloses a multi-mode heterogeneous computing processing system, and belongs to the technical field of embedded systems and high-performance computing. The system comprises a Chengteng 310P processor and Xilinx Zynq UltraScale +FPGA which form a heterogeneous computing core, integrates an LPDDR4x memory, an eMMC memory, various high-speed interfaces and a power management module, and is connected with an external functional module through a 688PIN BGA connector. The system supports a plurality of communication protocols such as SERDES high-speed serial communication, multi-channel gigabit Ethernet, USB 3.1, SATA, SDI video interfaces and the like, fully exerts the AI reasoning capability of Chengteng 310P and the hardware programmability of the FPGA, has strong data processing capability and flexible expansibility, and is suitable for application scenes such as video encoding and decoding, artificial intelligence reasoning, industrial control and the like.

Inventors

  • TANG YUMEI
  • ZHU BIN
  • HUANG SIYU
  • LU HOUBING
  • SHAO LI
  • YU HAO
  • ZHOU QUAN

Assignees

  • 中国人民解放军国防科技大学

Dates

Publication Date
20260508
Application Date
20251206

Claims (10)

  1. 1. A multi-modal heterogeneous computing processing system, the system comprising: The system comprises a main processing unit, an embedded processor, a control unit and a control unit, wherein the embedded processor is used for executing system control, task scheduling and AI reasoning calculation and adopts a Santeng 310P processor; The field programmable gate array is used as a co-processing unit and used for realizing hardware acceleration and interface expansion, and adopts a Xilinx Zynq UltraScale +FPGA combined form; The memory module comprises an LPDDR4x memory, an eMMC memory and an SPI NOR Flash; The high-speed interface module comprises a SERDES interface, a PCIe interface and a USB 3.1 interface; a network communication module; including a plurality of gigabit ethernet interfaces; The external function module is connected with the external function module through a 688PIN BGA connector; and the power management module is used for providing stable power supply for all parts of the system.
  2. 2. The multi-modal heterogeneous computing processing system of claim 1, wherein the embedded processor is coupled to the field programmable gate array via a high-speed bus, the two comprising a master-slave cooperative heterogeneous computing architecture, wherein the embedded processor runs an operating system and applications, and wherein the field programmable gate array implements hardware acceleration and interface expansion.
  3. 3. The multi-modal heterogeneous computing processing system of claim 2, wherein the memory module comprises 12 sets of LPDDR4x memory, 64GB eMMC memory, and SPI NOR Flash, connected to the embedded processor, field programmable gate array, respectively, through DDRC, eMMC, and SFC interfaces.
  4. 4. A multi-modal heterogeneous computing processing system as set forth in claim 3 wherein said high-speed interface module includes: four groups of SERDES interfaces, M2.0-M2.3, M2.4-M2.5, M3 and M4 respectively; PCIe to USB 3.1 controller; providing two USB 3.1 interfaces; SATA interface, and is connected with the field programmable gate array through SERDES M4.
  5. 5. The multi-modal heterogeneous computing processing system of claim 4 wherein the SERDES M2.4-M2.5 interface is coupled to a video codec card supporting SDI video input and output, the video codec processing being performed by an embedded processor, and the field programmable gate array being configured to perform video data scheduling.
  6. 6. The system of claim 5, wherein the network communication module comprises three gigabit ethernet interfaces, each implemented via an RTL8521 PHY chip, wherein one of the interfaces is a management interface, and the embedded processor performs network protocol processing.
  7. 7. The multi-modal heterogeneous computing processing system as set forth in claim 6 further comprising an RTC real time clock module, an INA226 power monitor chip, an LM75 temperature sensor, and peripheral devices connected via IIC0, IIC2 buses.
  8. 8. The multi-modal heterogeneous computing system of claim 7, further comprising a UART0 debug serial port, a UART1 RS485 interface, a UART2 RS232 interface, and a PWM controlled cooling fan.
  9. 9. The multi-modal heterogeneous computing processing system of claim 8, wherein the power management module comprises a PSIP power input subsystem, a VRD+DRMOS voltage regulator, and a PMU6421 power management unit.
  10. 10. A method of data processing, the method being implemented by a multi-modal heterogeneous computing processing system according to any one of claims 1-9, the method comprising: Receiving external data through the 688PIN BGA connector; the embedded processor performs system control, task scheduling and AI reasoning calculation; the field programmable gate array carries out hardware acceleration processing and interface data exchange; and the dynamic power consumption control of the system is realized through the power management module.

Description

Multi-mode heterogeneous computing processing system Technical Field The invention belongs to the technical field of embedded systems and high-performance computing, and particularly relates to a multi-mode heterogeneous computing processing system. Background With the rapid development of artificial intelligence, internet of things and industry 4.0 technology, modern embedded systems put higher demands on processing power, energy efficiency ratio and interface richness. The traditional single-architecture processing system has the defects that (1) the processing capability is limited, a single processor is difficult to simultaneously meet the requirements of control tasks, AI reasoning and real-time data processing, (2) the energy efficiency ratio is low when a general processor processes specific tasks, (3) the interface expansibility is poor, the fixed architecture is difficult to adapt to diversified peripheral interface requirements, and (4) the system flexibility is insufficient, and the computing resources are difficult to dynamically adjust according to application scenes. Disclosure of Invention The invention aims to provide a multi-mode heterogeneous computing processing system, which aims to solve the problems of limited processing capacity, low energy efficiency ratio and poor interface expansibility in the prior art. The first aspect of the present invention discloses a multi-modal heterogeneous computing processing system, the system comprising: The system comprises a main processing unit, an embedded processor, a control unit and a control unit, wherein the embedded processor is used for executing system control, task scheduling and AI reasoning calculation and adopts a Santeng 310P processor; The field programmable gate array is used as a co-processing unit and used for realizing hardware acceleration and interface expansion, and adopts a Xilinx Zynq UltraScale +FPGA combined form; The memory module comprises an LPDDR4x memory, an eMMC memory and an SPI NOR Flash; The high-speed interface module comprises a SERDES interface, a PCIe interface and a USB 3.1 interface; a network communication module; including a plurality of gigabit ethernet interfaces; The external function module is connected with the external function module through a 688PIN BGA connector; and the power management module is used for providing stable power supply for all parts of the system. Preferably, the embedded processor is connected with a field programmable gate array through a high-speed bus, and the embedded processor and the field programmable gate array form a master-slave cooperative heterogeneous computing architecture, wherein the embedded processor runs an operating system and an application program, and the field programmable gate array realizes hardware acceleration and interface expansion. Preferably, the storage module comprises 12 sets of LPDDR4x memory, 64GB eMMC memory and SPI NOR Flash, and is connected with the embedded processor and the field programmable gate array through DDRC, EMMC and SFC interfaces respectively. Preferably, the high-speed interface module includes: four groups of SERDES interfaces, M2.0-M2.3, M2.4-M2.5, M3 and M4 respectively; PCIe to USB 3.1 controller; providing two USB 3.1 interfaces; SATA interface, and is connected with the field programmable gate array through SERDES M4. Preferably, the SERDES M2.4-M2.5 interface is connected with a video codec card to support SDI video input and output, the embedded processor performs video codec processing, and the field programmable gate array is used for executing video data scheduling. Preferably, the network communication module comprises three gigabit ethernet interfaces, which are respectively implemented through RTL8521 PHY chips, wherein one of the gigabit ethernet interfaces is a management network interface, and the embedded processor performs network protocol processing. Preferably, the system further comprises an RTC real-time clock module, an INA226 power monitoring chip, an LM75 temperature sensor, and peripheral devices connected through IIC0 and IIC2 buses. Preferably, the system further comprises a UART0 debugging serial port, a UART1 RS485 interface, a UART2 RS232 interface and a PWM controlled cooling fan. Preferably, the power management module comprises a PSIP power input subsystem, a VRD+DRMOS voltage regulator, and a PMU6421 power management unit. A second aspect of the present invention discloses a data processing method, which is implemented by a multi-mode heterogeneous computing processing system according to the first aspect of the present invention, and the method includes: Receiving external data through the 688PIN BGA connector; the embedded processor performs system control, task scheduling and AI reasoning calculation; the field programmable gate array carries out hardware acceleration processing and interface data exchange; and the dynamic power consumption control of the system is realized through the po