Search

CN-121996600-A - Information transmission method, device, equipment and medium

CN121996600ACN 121996600 ACN121996600 ACN 121996600ACN-121996600-A

Abstract

The information transmission method, device, equipment and medium comprise the steps of clearing a first unprocessed request on an internal bus connected with a PCIE controller if determining that the PCIE equipment which needs to be communicated with the PCIE controller has a fault, sending a reset command to the PCIE controller to enable the PCIE controller to complete reset, acquiring a second request transmitted from an interface of the internal bus in a period from the state of a data link layer of the PCIE controller to the connection state when the PCIE controller completes reset, and feeding back a simulation response result of the second request to a sender of the second request. In this embodiment, after the PCIE controller is reset and in a period when the data link layer is not successfully established, a second request generated inside the chip is subjected to an analog response, so as to avoid a phenomenon that an internal bus is blocked.

Inventors

  • CAI FEI

Assignees

  • 龙芯中科技术股份有限公司

Dates

Publication Date
20260508
Application Date
20251216

Claims (13)

  1. 1. An information transmission method, comprising: If the PCIE equipment which needs to be communicated with the high-speed serial computer expansion bus standard PCIE controller is determined to have a fault, the first unprocessed request on an internal bus connected with the PCIE controller is emptied; Sending a reset command to the PCIE controller so that the PCIE controller can complete reset; And in the period from the completion of the reset of the PCIE controller to the switching of the state of the data link layer of the PCIE controller to the connection state, acquiring a second request transmitted from an interface of the internal bus, and feeding back an analog response result of the second request to a sender of the second request, wherein the slave interface is an interface for receiving a request for requesting to access the PCIE device from the internal bus.
  2. 2. The method of claim 1, wherein the determining that a PCIE device that needs to communicate with a PCIE controller is faulty comprises: if the specific condition exists, determining that PCIE equipment which needs to communicate with the PCIE controller has faults; Wherein the specific condition comprises one or more of a first condition, a second condition, a third condition, a fourth condition and a fifth condition; the first situation is that the state of the data link layer of the PCIE controller is switched from a connected state to a disconnected state; The second condition is that the link state of the physical layer of the PCIE controller is switched from a normal working state to a device detection state; the third condition is that when the state of the data link layer is a connection state, the token waiting time of a third request is larger than a first preset value; The fourth situation is that the PCIE controller receives a reset command; the fifth condition is that the response waiting time corresponding to the fourth request is larger than a second preset value; the token waiting time is the waiting time for waiting for the PCIE equipment to provide a token supporting the PCIE controller to send the third request; the fourth request is a non-reporting request sent to the PCIE device based on the slave interface of the internal bus and the PCIE controller, and the response waiting time is a duration for waiting for the PCIE device to return response data or response requested by the fourth request.
  3. 3. The method of claim 1, wherein the flushing the first request transmitted on the internal bus to which the PCIE controller is connected comprises: And if the first request is a write request on a main interface of the internal bus, sending a fifth request to a receiver of the first request to empty the first request, wherein the fifth request is used for indicating writing preset data, and the main interface is an interface on the internal bus for transmitting an access request sent by the PCIE controller.
  4. 4. The method of claim 1, wherein the flushing the first request transmitted on the internal bus to which the PCIE controller is connected comprises: And if the first request is a read request or an atomic operation request on a main interface of the internal bus, sending the first request to a receiver of the first request, and receiving response data of the first request sent by the receiver of the first request so as to empty the first request.
  5. 5. The method of claim 1, wherein the flushing the first request transmitted on the internal bus to which the PCIE controller is connected comprises: And if the first request is a write request on a slave interface of the internal bus, acquiring the first request, and feeding back a write response to a sender of the first request so as to empty the first request.
  6. 6. The method of claim 1, wherein the flushing the first request transmitted on the internal bus to which the PCIE controller is connected comprises: if the first request is a read request or an atomic operation request on a slave interface of the internal bus, acquiring the first request, and feeding back an analog data response to a sender of the first request according to target data acquired by the first request so as to empty the first request, wherein the analog data response carries invalid data, and the data length of the invalid data is the same as that of the target data.
  7. 7. The method of any of claims 1-6, wherein the sending a reset command to the PCIE controller comprises: And if all the write requests on the internal bus are determined to be emptied and all the data requests on the internal bus are determined to be emptied, sending a reset command to the PCIE controller, wherein the data requests are read requests or atomic operation requests.
  8. 8. The method of claim 7, wherein the determining that all write requests on the internal bus are flushed comprises: The method comprises the steps of obtaining first record information corresponding to a first target interface in an internal bus, wherein the first target interface is a master interface of the internal bus for transmitting write requests or a slave interface of the internal bus for transmitting write requests, the first record information is used for recording whether each write request transmitted under the first target interface correspondingly receives write responses or not, or the first record information is used for recording a count value, the count value is subjected to 1 adding operation after the first target interface successfully transmits one write request, and is subjected to 1 subtracting operation after the first target interface successfully receives one write response; if the first record information indicates that all the write requests transmitted by the first target interface are answered, determining that all the write requests on the internal bus are emptied.
  9. 9. The method of claim 7, wherein the determining that all data requests on the internal bus are emptied comprises: The method comprises the steps of acquiring second record information corresponding to a second target interface in the internal bus, wherein the second target interface is a master interface of the internal bus or a slave interface of the internal bus for transmitting data requests, and the second record information is used for indicating whether all data requested by each data request transmitted under the second target interface are acquired or not; And if the second record information represents that all the data requests transmitted by the second target interface acquire the requested data, determining that all the data requests on the internal bus are emptied.
  10. 10. An information transmission apparatus, characterized in that the apparatus comprises: The clearing unit is used for clearing an unprocessed first request on an internal bus connected with the PCIE controller if determining that the PCIE equipment which needs to be communicated with the high-speed serial computer expansion bus standard PCIE controller has a fault; The first sending unit is used for sending a reset command to the PCIE controller so that the PCIE controller can complete reset; the obtaining unit is used for obtaining a second request transmitted from an interface of the internal bus in a period from the completion of resetting of the PCIE controller to the switching of the state of the data link layer of the PCIE controller to the connection state; the second sending unit is used for feeding back the simulation response result of the second request to the sender of the second request; the slave interface is an interface for receiving a request from an internal bus for accessing the PCIE device.
  11. 11. The chip is characterized by comprising a PCIE controller, the information transmission device according to claim 10 and at least one functional module, wherein the PCIE controller is connected with the functional module inside the chip through the information transmission device.
  12. 12. An electronic device comprising a processor and a memory communicatively coupled to the processor; The memory stores computer-executable instructions; The processor executes computer-executable instructions stored in the memory to implement the method of any one of claims 1 to 9.
  13. 13. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor are adapted to carry out the method of any one of claims 1 to 9.

Description

Information transmission method, device, equipment and medium Technical Field The present application relates to the field of electronics, and in particular, to an information transmission method, apparatus, device, and medium. Background Currently, a high-speed serial computer expansion bus standard (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, abbreviated as PCIE) bus is a peripheral bus commonly used in computer systems. In addition, a PCIE controller is usually built into a chip of the computer system. The functional modules inside the chip can be connected with the PCIE controller by using an internal bus, and the PCIE controller performs conversion processing of an internal bus protocol and the PCIE protocol, so that the functional modules inside the chip can communicate with external PCIE equipment (namely, outside the chip) through the PCIE controller. In the related art, after a link of the PCIE controller (i.e., a link connected to the PCIE device) fails, a reset operation may be performed on the PCIE controller, so that the PCIE controller may reestablish the link after being reset. However, if the PCIE controller is reset, the link still cannot be successfully established, and the PCIE controller receives again an access request from the functional module inside the chip to request to access the external PCIE device, because the link is not yet established successfully, the access request cannot be successfully sent, and the functional module is always in a state of waiting for the response of the access request, so that the internal bus is blocked. Disclosure of Invention The application provides an information transmission method, an information transmission device, information transmission equipment and an information transmission medium, which are used for reducing the risk of blocking an internal bus of a chip. In a first aspect, the present application provides an information transmission method, including: If the PCIE equipment which needs to be communicated with the high-speed serial computer expansion bus standard PCIE controller is determined to have a fault, the first unprocessed request on an internal bus connected with the PCIE controller is emptied; Sending a reset command to the PCIE controller so that the PCIE controller can complete reset; And in the period from the completion of the reset of the PCIE controller to the switching of the state of the data link layer of the PCIE controller to the connection state, acquiring a second request transmitted from an interface of the internal bus, and feeding back an analog response result of the second request to a sender of the second request, wherein the slave interface is an interface for receiving a request for requesting to access the PCIE device from the internal bus. In one example, the determining that the PCIE device that needs to communicate with the PCIE controller has a failure includes: if the specific condition exists, determining that PCIE equipment which needs to communicate with the PCIE controller has faults; Wherein the specific condition comprises one or more of a first condition, a second condition, a third condition, a fourth condition and a fifth condition; the first situation is that the state of the data link layer of the PCIE controller is switched from a connected state to a disconnected state; The second condition is that the link state of the physical layer of the PCIE controller is switched from a normal working state to a device detection state; the third condition is that when the state of the data link layer is a connection state, the token waiting time of a third request is larger than a first preset value; The fourth situation is that the PCIE controller receives a reset command; the fifth condition is that the response waiting time corresponding to the fourth request is larger than a second preset value; the token waiting time is the waiting time for waiting for the PCIE equipment to provide a token supporting the PCIE controller to send the third request; the fourth request is a non-reporting request sent to the PCIE device based on the slave interface of the internal bus and the PCIE controller, and the response waiting time is a duration for waiting for the PCIE device to return response data or response requested by the fourth request. In one example, the flushing the first request transmitted on the internal bus connected to the PCIE controller includes: And if the first request is a write request on a main interface of the internal bus, sending a fifth request to a receiver of the first request to empty the first request, wherein the fifth request is used for indicating writing preset data. In one example, the flushing the first request transmitted on the internal bus connected to the PCIE controller includes: And if the first request is a read request or an atomic operation request on a main interface of the internal bus, sending the first request to a receiver of the first request, and receiving