CN-121996601-A - High-speed serialization implementation method based on processor parallel bus

CN121996601ACN 121996601 ACN121996601 ACN 121996601ACN-121996601-A

Abstract

The invention belongs to the technical field of computer interfaces, and particularly relates to a high-speed serialization realization method based on a processor parallel bus. The method comprises the steps of 1, generating a high-speed clock by a monitoring branch FPGA in the process of writing operation of the monitoring branch processor, converting serial addresses and data into Manchester codes when the processor initiates a writing command, sending the coded addresses and data to an instruction branch FPGA through each data line, and 2, after receiving the addresses, an instruction receiving module of the instruction branch FPGA in the process of reading operation of the monitoring branch processor, uniformly arranging the data to be sent on a plurality of receiving data lines in series, and then converting the data sent by a band into Manchester codes through a coding module and then sending the Manchester codes to the monitoring branch FPGA.

Inventors

CHEN SHUXUAN
PEI FUSUI
HU WENXIANG
YANG GUANG
HEI RUNSHAN
LIU RUIZHUO
JIANG TAO
YAN JIACHENG
Jing Zhengdong

Assignees

中国航空工业集团公司西安飞行自动控制研究所

Dates

Publication Date: 20260508
Application Date: 20251224

Claims (9)

1. A method for implementing high-speed serialization based on a processor parallel bus, wherein the method is used for implementing high-speed serialization of an instruction branch and a monitoring branch, the instruction branch comprises an instruction sending module and an instruction receiving module, the monitoring branch comprises a monitoring sending module and a monitoring receiving module, and the method comprises: Step 1, in the process of writing operation of a monitoring branch processor, a monitoring branch FPGA generates a high-speed clock, when the processor initiates a writing command, serial addresses and data are converted into Manchester codes, and the coded addresses and data are sent to an instruction branch FPGA through each data line; And 2, in the process of reading operation of the monitoring branch processor, after receiving the address, the instruction receiving module of the instruction branch FPGA uniformly arranges the data to be transmitted on a plurality of receiving data lines in series, and then converts the data transmitted by the band into Manchester codes through the coding module and transmits the Manchester codes to the monitoring branch FPGA.
2. The method according to claim 1, characterized in that step 1, in particular: Step 11, generating a synchronous clock through a local clock after the reset signal of the monitoring branch FPGA is invalid, and sending the synchronous clock to the instruction branch FPGA; Step 12, the data conversion module monitors the processor, and when the processor has no read-write command, the coding module is controlled to continuously send out an idle state signal; Step 13, when the processor initiates a write command, a chip selection signal is pulled down, write enable is pulled down, read enable is continuously high, the processor sends effective address and data, when the data conversion module detects that the write command is a write operation, the data conversion module converts the write command into the read write enable for the identification of the instruction branch FPGA, the address and the data are arranged on each serial data line through a shift register, the coding module converts the serial data into Manchester codes, and the coded data are sent to the instruction branch FPGA through each data line; And 14, after receiving the data sent by the monitoring branch FPGA, the instruction receiving module decodes the write data by using a synchronous clock to obtain serial data of each path, after synchronizing by using a local clock, stores the coding format of write command, address and data write operation in a shift register, and finally analyzes the read enable, address and data through serial-parallel conversion, and sends the received data to the internal module to complete write operation once.
3. The method according to claim 2, wherein in step 11, the frequency of the transmitted synchronization clock is 100MHz.
4. The method of claim 3, wherein the idle signal is a logic 1 for 2 clock cycles, a logic 0 for 2 clock cycles, and is continuously cycled in step 12.
5. The method according to claim 4, wherein step 2 specifically comprises: step 21, reading operation needs to monitor the branch FPGA to send an address to the instruction branch FPGA, waiting for feedback of read data; Step 22, after receiving the address, the instruction receiving module of the instruction branch FPGA sends the address to the internal module through the instruction receiving module, the internal module sends data to the instruction sending module, the data conversion module of the instruction sending module arranges the data to be sent in the shift register, the feedback data format is arranged uniformly in series on a plurality of receiving data lines, and then the feedback data format is converted into Manchester code through the coding module and then sent to the monitoring branch FPGA; And step 23, after the monitoring receiving module receives the data, identifying the starting marks of 3 high levels and 3 low levels, decoding the starting marks through the decoding module after the starting marks are identified, and finally converting the starting marks into parallel data through a shift register in the data conversion module and transmitting the parallel data to a data bus of a processor to finish one-time reading operation.
6. The method according to claim 5, wherein step 21 is specifically: When the processor initiates a read command, the chip select signal is pulled low, the write enable is continuously high, the read enable is pulled low, the processor sends in an effective address, and the feedback of the read data is waited.
7. The method according to claim 6, wherein step 21 is specifically: when the data conversion module of the monitoring and transmitting module detects that the data is read, the data conversion module converts a read command into read-write enabling, addresses are uniformly arranged in a plurality of transmitting data lines in series, address information is converted into Manchester codes, and the Manchester codes are transmitted to the instruction branch FPGA.
8. The method of claim 7, wherein in step 21, the read/write enable is maintained at 3 clock low and 3 clock high.
9. The method of claim 8, wherein in step 22, the start flag of the feedback data is high for 3 clock cycles and low for 3 clock cycles, and X is an arbitrary value.

Description

High-speed serialization implementation method based on processor parallel bus Technical Field The invention belongs to the technical field of computer interfaces, and particularly relates to a high-speed serialization realization method based on a processor parallel bus. Background The parallel bus of the processor is used for the processor to access the peripheral, has wide application in various computer systems, and has the advantages of high transmission speed, low asynchronous transmission time sequence requirement, large transmission data quantity and the like. However, since the processor bus is a parallel bus, there are disadvantages such as a large number of signals, a large wiring difficulty, and a parallel data bus being susceptible to external interference. Aiming at the defects, when a processor needs to access on-board equipment or devices, the high-speed serialization of parallel transmission media between boards can be considered by using anti-crosstalk code value codes, namely, a processor bus is converted into a high-speed serial bus and then is communicated with other board cards, and then the high-speed serial bus is converted into a bus interface aiming at the processor on the devices, so that the read-write operation of the processor across the devices is realized. Disclosure of Invention The invention aims to: The method comprises the steps of converting the parallel bus (comprising enabling, address and data) of a processor into a high-speed serial bus through FPGA logic in an application scene of writing and accessing an external device by the processor, accessing other devices in a serial transmission mode, converting enabling and address signals of the processor into the high-speed serial bus in an application scene of reading and accessing the external device by the processor, waiting for device feedback data, converting the high-speed serial bus data into the processor parallel data and sending the processor parallel data to the processor, and achieving the effects of simplifying wiring, reducing design difficulty and improving communication reliability. The technical scheme is as follows: A method for implementing high-speed serialization of a processor parallel bus, the method being used for implementing high-speed serialization of an instruction branch and a monitoring branch, the instruction branch including an instruction sending module and an instruction receiving module, the monitoring branch including a monitoring sending module and a monitoring receiving module, the method comprising: Step 1, in the process of writing operation of a monitoring branch processor, a monitoring branch FPGA generates a high-speed clock, when the processor initiates a writing command, serial addresses and data are converted into Manchester codes, and the coded addresses and data are sent to an instruction branch FPGA through each data line; And 2, in the process of reading operation of the monitoring branch processor, after receiving the address, the instruction receiving module of the instruction branch FPGA uniformly arranges the data to be transmitted on a plurality of receiving data lines in series, and then converts the data transmitted by the band into Manchester codes through the coding module and transmits the Manchester codes to the monitoring branch FPGA. Further, step 1 specifically comprises: Step 11, generating a synchronous clock through a local clock after the reset signal of the monitoring branch FPGA is invalid, and sending the synchronous clock to the instruction branch FPGA; Step 12, the data conversion module monitors the processor, and when the processor has no read-write command, the coding module is controlled to continuously send out an idle state signal; Step 13, when the processor initiates a write command, a chip selection signal is pulled down, write enable is pulled down, read enable is continuously high, the processor sends effective address and data, when the data conversion module detects that the write command is a write operation, the data conversion module converts the write command into the read write enable for the identification of the instruction branch FPGA, the address and the data are arranged on each serial data line through a shift register, the coding module converts the serial data into Manchester codes, and the coded data are sent to the instruction branch FPGA through each data line; And 14, after receiving the data sent by the monitoring branch FPGA, the instruction receiving module decodes the write data by using a synchronous clock to obtain serial data of each path, after synchronizing by using a local clock, stores the coding format of write command, address and data write operation in a shift register, and finally analyzes the read enable, address and data through serial-parallel conversion, and sends the received data to the internal module to complete write operation once. Further, in step 11, the frequency of the transmitted synchroniz