CN-121996602-A - Master and slave verification method based on bus communication, chip, computer readable storage medium and printing system

Abstract

The invention discloses a master and slave verification method based on bus communication, which comprises the steps of receiving a first instruction from a host, wherein the first instruction is used for indicating the slave to carry out verification calculation, receiving a first request from the host, judging whether a preset first event occurs, sending a first mark to the host if the preset first event occurs, receiving a second request from the host, judging whether a preset second event occurs, and sending an algorithm result to the host in response to judging that the preset second event occurs, wherein the slave is configured to not send the algorithm result until the preset second event does not occur. The slave is configured to not send an algorithm result before judging that the preset second event does not occur, so that the slave is prevented from exposing safety information or entering an unexpected state due to program conflict, and the safety of the system is improved.

Inventors

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Assignees

• 广州众诺微电子有限公司

Dates

Publication Date

20260508

Application Date

20260115

Claims (20)

1. 1. A method for checking a master and a slave based on bus communication, wherein the method is applied to the slave, the slave comprises a second control part and a second memory, and the method comprises: receiving a first instruction from a host, wherein the first instruction is used for indicating the slave to perform verification calculation; Receiving a first request from the host; judging whether a preset first event occurs or not; If the preset first event occurs, a first mark is sent to the host, wherein the first mark is used for indicating that the slave is in a first waiting state for processing the first instruction; Receiving a second request from the host; judging whether the preset second event occurs or not, and Transmitting an algorithm result to the host in response to determining that the preset second event occurs; wherein the slave is configured to not send the algorithm result until it is determined that the preset second event does not occur.
2. 2. The method of claim 1, wherein prior to the step of receiving a second request from the host, the method further comprises: Receiving a second instruction from the host and sending first information to the host for the second instruction; Wherein the second instruction is configured to trigger the slave to prepare to respond to the second request.
3. 3. The method of claim 1, wherein after the step of determining whether the preset first event occurs, further comprising: if the preset first event is judged not to occur, second information is sent to the host; The second information is a negative character, which indicates that the communication bus is in a locked state, and the slave returns to execute the step of receiving the first request from the host after sending the second information.
4. 4. The method of claim 2, wherein after the step of determining whether the preset second event occurs, further comprising: If the preset second event is judged not to occur, a second mark is sent to the host; the second mark is used for indicating that the slave is in a second waiting state of processing the first instruction or waiting for the occurrence of the preset second event; And after the secondary machine sends the second mark, returning to the step of executing the second instruction received from the primary machine.
5. 5. The method of claim 1, wherein the first instruction includes an algorithm parameter N, the algorithm result being calculated by the slave based on the algorithm parameter N; The preset second event is a time attribute event, and the judging whether the preset second event occurs includes: analyzing the first instruction to obtain the algorithm parameter N; Determining target response time corresponding to the preset second event according to the algorithm parameter N as a dynamic adjustment factor; And judging whether the current time reaches the target response time or not.
6. 6. The method of claim 5, wherein determining the target response time corresponding to the preset second event comprises: Calculating the target response time T2 using the formula t2=t1+k×n; Wherein T1 is a basic preset time, K is a preset coefficient, and N is the algorithm parameter; and hiding the real algorithm calculation completion time by the slave before the target response time T2 arrives.
7. 7. The method of claim 1, wherein the first instruction comprises an address code and a write operation code, and wherein the first request and the second request comprise an address code and a read operation code; the first information and the first flag include a validation character; the algorithm results include verification data generated based on the first instruction.
8. 8. The method of claim 1, wherein the determining whether the predetermined first event occurs comprises: And judging whether the time elapsed from the transmission of the response information for the first instruction or the reception of the first instruction reaches a first preset time threshold.
9. 9. The method according to claim 1, wherein the method further comprises: upon receiving the first request from the host, recording a received timestamp and a source address; Judging whether the number of times of receiving the first request from the same source address within a defined time stamp exceeds a preset threshold M; And if the preset threshold M is exceeded, locking the source address, and rejecting subsequent read requests or write requests.
10. 10. The method of claim 1, wherein after the step of sending the algorithm result to the host computer in response to determining that the preset second event occurs, further comprising: and automatically clearing the relevant state of the first instruction and the algorithm result.
11. 11. A chip, comprising: a communication interface configured to communicate with a host via a bus; A second memory for storing instructions and data, and A second control section connected to the communication interface and the second memory, the second control section configured to perform operations of: receiving a first instruction from the host through the communication interface; Receiving a first request from the host through the communication interface; judging whether a preset first event occurs or not; if the preset first event occurs, a first mark is sent to the host computer through the communication interface, wherein the first mark is used for indicating that the slave computer is in a first waiting state for processing the first instruction; receiving a second request from the host through the communication interface; judging whether the preset second event occurs or not, and Transmitting an algorithm result to the host through the communication interface in response to determining that the preset second event occurs; wherein the second control section is configured not to send the algorithm result until it is determined that the preset second event does not occur.
12. 12. The chip of claim 11, wherein the second control portion is further configured to: if the preset first event is judged not to occur, second information is sent to the host; the second information is a negative character, which indicates that the communication bus is in a locked state, and the slave returns to execute the operation of receiving the first request from the host after sending the second information.
13. 13. The chip of claim 11, wherein the second control portion is further configured to: If the preset second event is judged not to occur, a second mark is sent to the host; the second mark is used for indicating that the slave is in a second waiting state of processing the first instruction or waiting for the occurrence of the preset second event; and the slave returns to execute the operation of receiving the second instruction from the host after sending the second mark.
14. 14. The chip of claim 11, wherein the first instruction includes an algorithm parameter N, and the algorithm result is calculated by the slave based on the algorithm parameter N; The second preset event is a time attribute event, and when judging whether the second preset event occurs, the second control part is configured to: analyzing the first instruction to obtain the algorithm parameter N; Determining target response time corresponding to the preset second event according to the algorithm parameter N as a dynamic adjustment factor; And judging whether the current time reaches the target response time or not.
15. 15. The chip of claim 11, wherein the second control portion determining whether a preset first event occurs comprises: And judging whether the time elapsed from the transmission of the response information for the first instruction or the reception of the first instruction reaches a first preset time threshold.
16. 16. The chip of claim 11, wherein the second control portion is further configured to: upon receiving the first request from the host, recording a received timestamp and a source address; Judging whether the number of times of receiving the first request from the same source address within a defined time stamp exceeds a preset threshold M; and if the preset threshold M is exceeded, locking the source address, and rejecting subsequent read requests or write requests. .
17. 17. The chip of claim 11, wherein the second control portion is further configured to: after the response to the judgment that the preset second event occurs, sending an algorithm result to the host through the communication interface, the method further comprises: and automatically clearing the relevant state of the first instruction and the algorithm result.
18. 18. A computer readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, implements the method according to any one of claims 1 to 10.
19. 19. A printing system comprising a host computer and a chip as claimed in any one of claims 11 to 17; The host includes a first control portion and a first memory, the first control portion being configured to send the first instruction, the first request, and the second request to the chip, and to receive the algorithm result to verify the legitimacy of the chip.
20. 20. The printing system of claim 19, wherein the host remains busy on the bus after receiving the first flag or the second flag or resends the first request or the second request after a predetermined time until the algorithm result is received.

Description

Master and slave verification method based on bus communication, chip, computer readable storage medium and printing system Technical Field The invention relates to the technical field of master and slave communication interaction based on bus communication, in particular to a master and slave verification method, a chip, a computer readable storage medium and a printing system based on bus communication. Background Many systems have replaceable components necessary for system operation. The replaceable component is often a device that contains consumable materials that are consumed with each use of the system. Such systems typically include, for example, a water drinking device with a replaceable cartridge, a medical system with a replaceable supply dispensing medication, a printing system with a replaceable supply dispensing fluid or solids, and the like. Verifying that the alternative provisioning device is a trusted device from a legitimate manufacturer may help system users avoid interfacing with defective or counterfeit devices. As described above, verifying the trustworthiness of the replaceable supply device for use in certain systems may help system users avoid problems associated with unintended use of defective or counterfeit devices. For example, in printing systems employing consumable toner or ink cartridges, inadvertent replacement of the ink cartridge with a counterfeit ink cartridge can lead to a variety of problems ranging from poor quality printouts to leaking ink cartridges that can damage the printing system. Methods of authenticating a replaceable device generally include employing methods involving strong authentication using a secret key known by a security micro-control unit on a replaceable supply device (capable of dispensing a fluid or a solid or the like) and a host device (e.g., an image forming device). If the replaceable device can prove to the host that it is a legitimate device by issuing a proper response (typically an authentication response to a key), the host will infer that the device is the original manufacturer and authenticate the device. One weakness of this authentication method is that it relies on the ability of the system to hold secret keys. In case an attacker can recover all keys from the host or the alternative device, it can store the keys in the micro-control of the illegitimate alternative provisioning device so that it produces the correct response that would be the same as the trusted device of the original manufacturer. Disclosure of Invention In order to solve the problems that in the prior art, a slave leaks safety information or enters an unexpected state due to program conflict, and a malicious host occupies bus resources through a high-frequency request. In a first aspect, the application provides a master-slave verification method based on bus communication, which is applied to a slave, wherein the slave comprises a second control part and a second memory, the method comprises the steps of receiving a first instruction from a host, the first instruction is used for indicating the slave to perform verification calculation, receiving a first request from the host, judging whether a preset first event occurs, sending a first mark to the host if the preset first event occurs, the first mark is used for indicating the slave to be in a first waiting state of processing the first instruction, receiving a second request from the host, judging whether a preset second event occurs, and sending an algorithm result to the host in response to judging that the preset second event occurs, wherein the slave is configured not to send the algorithm result until the preset second event does not occur. In particular, the slave is configured to not send the algorithm result before judging that the preset second event (e.g., the dynamically calculated target response time) does not occur, but maintains the communication connection through the intermediate flag or protects the bus through the negative character, so that the safety information is prevented from being exposed or the slave enters an unexpected state due to program conflict while ensuring the integrity of the communication protocol, and the safety of the system is improved. In a second aspect, the application provides a chip comprising a communication interface configured to communicate with a host computer via a bus, a second memory for storing instructions and data, and a second control part connected to the communication interface and the second memory, the second control part configured to receive a first instruction from the host computer via the communication interface, receive a first request from the host computer via the communication interface, determine whether a preset first event occurs, send a first flag to the host computer via the communication interface if the preset first event occurs, the first flag being used for indicating that the slave computer is in a first waiting state in which t