CN-121996603-A - Cascade chip with serial cascade communication interface and serial transmission assembly thereof

CN121996603ACN 121996603 ACN121996603 ACN 121996603ACN-121996603-A

Abstract

The invention provides a cascade chip with a serial cascade communication interface and a serial transmission assembly thereof, which comprises the serial cascade communication interface, wherein the serial cascade communication interface comprises a serial data input interface and a clock signal input interface which are used for receiving input signals, and a serial data output interface and a clock signal output interface which are used for providing output signals and are connected to the next cascade chip, so that a chip selection signal interface is omitted. The cascade chip with the serial cascade communication interface introduces the serial cascade communication interface of the double-line cascade for the application of high polling rate of the keyboard, does not need chip selection signals, realizes the characteristics of automatic time sequence optimization and low delay through a buffer transmission mode and a direct transmission mode, ensures that wiring is concise and flexible, and has high transmission efficiency, safety and low power consumption.

Inventors

ZHU TINGJUN
HOU MINGMING
WANG KAIFENG

Assignees

钰泰半导体股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260409

Claims (10)

1. The cascade chip with the serial cascade communication interface is characterized by comprising the serial cascade communication interface, wherein the serial cascade communication interface comprises a serial data input interface and a clock signal input interface which are used for receiving input signals, and a serial data output interface and a clock signal output interface which are used for providing output signals and are connected to the next cascade chip, and a chip selection signal interface is omitted.
2. The cascade chip with the serial cascade communication interface according to claim 1, wherein the cascade chip with the serial cascade communication interface is configured to transmit and execute an automatic serial number command to the cascade chip in a buffer transmission mode to realize automatic serial number of the cascade chip after the cascade chip is powered on, and automatically and uniformly switch to a through transmission mode to transmit and execute other commands after all the cascade chips are automatically numbered.
3. The cascade chip with serial cascade communication interface according to claim 2, wherein in the buffer transmission mode, the output signal of the serial data output interface is delayed by one field unit compared to the serial data input interface, the output signal of the clock signal output interface is delayed by half a clock period compared to the input signal of the clock signal input interface, and the time delayed by one field unit is used for automatically numbering the cascade chip.
4. The cascade chip with the serial cascade communication interface according to claim 2, wherein in the buffer transmission mode, the cascade chip with the serial cascade communication interface is set to acquire numbers of the number bits and serve as own numbers after receiving an automatic serial data input interface numbering command, and the numbers of the number bits are automatically added by 1 before outputting the automatic serial data input interface numbering command to the cascade chip so as to realize automatic numbering of the cascade chip.
5. The cascade chip with serial cascade communication interface according to claim 2, wherein the packet header of the automatic cascade chip numbering command stores the total number of cascade chips, and the total number of cascade chips is used for realizing automatic unified switching to a through transmission mode after all cascade chips are automatically numbered.
6. The cascade chip with the serial cascade communication interface as claimed in claim 5, wherein the cascade chip is configured to provide a clock with a total length equal to the total number of the cascade chips x the length of the field units from the outside when transmitting the command for automatically numbering the cascade chips in the buffer transmission mode, so that each cascade chip can complete the automatic numbering and determine the time when all the cascade chips are automatically numbered according to the serial numbers and the clock, and automatically and uniformly switch to the through transmission mode after all the cascade chips are automatically numbered.
7. The cascaded chip with the serial cascade communication interface as claimed in claim 2, wherein the cascaded chip with the serial cascade communication interface outputs the serial data in a clock rising edge synchronous manner in a through transmission mode, and a clock signal of the clock signal output interface is delayed by half a period compared to a clock signal of the clock signal input interface.
8. The cascaded chip with the serial cascade communication interface according to claim 2, wherein the transmission protocol of the cascaded chip with the serial cascade communication interface comprises five commands of automatically numbering the cascaded chip, broadcasting a write command to the cascaded chip, selecting a specific chip write command, selecting a specific chip read command, and a high-speed chip wake-up command.
9. The cascaded chip with the serial cascade communication interface of claim 8, wherein the automatic numbering of the cascaded chip commands comprises a start identifier, a command header, a sub-header, a numbering bit, and a termination identification bit; the broadcasting writing command to the cascade chip comprises a starting identifier, a command packet head, a data bit and a termination identification bit; The selected specific chip writing command comprises a starting identifier, a command packet header, a sub-packet header 0, a sub-packet header 1, data bits and a termination identification bit; the selected specific chip reading command comprises a starting identifier, a command packet header, a sub-packet header 0, a sub-packet header 1, data bits and a termination identification bit; The high-speed chip wake-up command comprises a start identifier, a command packet header, a sub-packet header 1 and a termination identification bit; Each of the start identifier, the command header, the sub-header 0, the sub-header 1, the number bits, and the termination identification bits is a field unit, and the length of the data bits is an integer multiple of the field unit.
10. A serial transmission module based on a cascade chip with a serial cascade communication interface, comprising an MCU chip and a plurality of cascade chips with serial cascade communication interfaces according to one of claims 1-9 serially cascade connected in sequence from the MCU chip.

Description

Cascade chip with serial cascade communication interface and serial transmission assembly thereof Technical Field The invention relates to the technical field of communication interfaces of electronic equipment, in particular to a cascade chip with a serial cascade communication interface and a serial transmission assembly thereof, which are oriented to high polling rate application scenes such as keyboards. Background Along with the vigorous development of the electronic competition industry, the response speed of electronic competition game players to keyboards is required to be higher and higher, the keyboard polling rate directly determines the operation delay, and the rapid response brings the advantage of even millisecond level, so that the winner and the winner of an electronic competition can be determined sometimes. Typically, the keyboard has 87, 104 and 108 keys, each key needs a separate IC chip, and in order to meet the requirement of high polling rate, the chip communication interface is required to support a high-speed, flexible and safe transmission mode. The conventional keyboard adopts a plurality of independent key ICs, and the conventional parallel interface or standard SPI (serial peripheral interface) interface has obvious defects of large number of chip selection signal lines, complex PCB wiring, accumulated cascading transmission delay, difficult alignment of time sequences, manual numbering of chips, low production efficiency, high power consumption caused by continuous power supply of clocks, and easy occurrence of time sequence drift and communication errors in multi-chip cascading, and cannot meet the requirements of high polling rate, low delay, low power consumption and simple wiring. Disclosure of Invention The invention aims to provide a cascade chip with a serial cascade communication interface and a serial transmission assembly thereof, which have the characteristics of high communication rate, simplified circuit layout, automatic time sequence optimization, low power consumption and high polling rate. In order to achieve the above objective, the present invention provides a cascade chip with a serial cascade communication interface, which includes a serial cascade communication interface, wherein the serial cascade communication interface includes a serial data input interface and a clock signal input interface for receiving an input signal, and a serial data output interface and a clock signal output interface for providing an output signal and connecting to a next cascade chip, so as to omit a chip select signal interface. The cascade chip with the serial cascade communication interface is arranged in such a way that after the cascade chip is electrified, the cascade chip is firstly transmitted and executed in a buffer transmission mode to automatically number the cascade chip so as to realize automatic numbering of the cascade chip, and after all the cascade chips are automatically and uniformly numbered, the cascade chip is automatically and uniformly switched into a direct transmission mode to transmit and execute other commands. In the buffer transmission mode, the output signal of the serial data output interface is delayed by one field unit compared with the serial data input interface, the output signal of the clock signal output interface is delayed by half a clock period compared with the input signal of the clock signal input interface, and the time of delaying by one field unit is used for automatically numbering the cascade chips. In the buffer transmission mode, the cascade chip with the serial cascade communication interface is arranged to acquire numbers of the number bits and serve as own numbers after receiving an automatic serial chip numbering command through the input serial data input interface, and to automatically add 1 to the numbers of the number bits before outputting the automatic serial chip numbering command through the serial data output interface so as to realize automatic serial numbering of the cascade chip. The sub-packet heads of the automatic numbering command for the cascade chips store the total number of the cascade chips, and the total number of the cascade chips is used for realizing automatic unified switching to a direct transmission mode after all the cascade chips are automatically numbered. The cascade chips are arranged in such a way that when the automatic serial number command of the cascade chips is transmitted in the buffer transmission mode, the clock with the total length equal to the total number of the cascade chips and the length of the field units is provided by the outside, so that each cascade chip can finish automatic serial number, the time when all the cascade chips finish automatic serial number is determined according to the serial number and the clock, and the cascade chips are automatically and uniformly switched into the direct transmission mode after the automatic serial number of all the cascade chips i