CN-121996605-A - Parallel access device, parallel access method, antenna component system, storage medium, and program product

Abstract

The present application relates to a parallel access apparatus, a parallel access method, an antenna assembly system, a storage medium, and a program product. The device comprises a processor, a logic controller and a plurality of executors, wherein the processor is connected with the logic controller through a bus and is connected with the executors, a target memory in the processor stores first space owner information, a space storage area in the logic controller stores second space owner information, the target memory is divided into the target memory at the processor side, the first space owner information is stored in the target memory and the second space owner information is stored in the space storage area at the logic controller side, the time is kept consistent, TLP messages generated by the control right of the processor for inquiring the space storage area are reduced, the problem of transmission blockage of the bus messages is effectively solved, access channels of tens of executors are not affected each other, real parallel access is realized, and the parallel access efficiency is greatly improved.

Inventors

• YU QIUJU

Assignees

• 大唐移动通信设备有限公司

Dates

Publication Date

20260508

Application Date

20241107

Claims (20)

1. 1. The parallel access device is characterized by comprising a processor, a logic controller and a plurality of executors, wherein the processor is connected with the logic controller through a bus; the processor is internally provided with a target memory, and first space owner information is stored in the target memory; a space storage area is arranged in the logic controller, and second space owner information is stored in the space storage area; The processor is used for detecting the control right of the space storage area according to the first space owner information when an access request is received, and carrying out data transmission with the logic controller through the bus under the condition that the control right is detected to belong to the processor; And the logic controller is used for detecting the control right of the space storage area according to the second space owner information, and performing data access with an executor to be accessed by the access request under the condition that the control right belongs to the logic controller.
2. 2. The apparatus of claim 1, wherein the processor is further configured to release control of the processor to the logical controller based on the first spatial owner information after data transfer with the logical controller over the bus; the logic controller is further used for releasing the control right of the logic controller to the processor according to the second space owner information after the logic controller performs data access with the executor to be accessed by the access request.
3. 3. The apparatus of claim 2, wherein the processor is configured to modify a first owner flag bit in the first spatial owner information from a first value to a second value when releasing control of the processor to the logical controller based on the first spatial owner information; correspondingly, when the processor releases the control right of the processor, the logic controller is further configured to modify a second owner flag bit in the second spatial owner information from the first value to the second value, where the first value indicates that the control right belongs to the processor, and the second value indicates that the control right belongs to the logic controller.
4. 4. The apparatus of claim 2, wherein the means for modifying the second owner flag bit in the second spatial owner information from the second value to the first value is configured to release control of the logical controller to the processor based on the second spatial owner information; correspondingly, the processor is further configured to modify a first owner flag bit in the first spatial owner information from the second value to the first value when the logic controller releases the control right of the logic controller.
5. 5. The apparatus of any of claims 1-4, wherein the processor further comprises a bus read-write driver and a plurality of application modules; the application module is used for receiving the access request and transmitting the access request to the bus read-write driver; The bus read-write driver is used for detecting the control right of the space storage area according to the first space owner information, and transmitting the data associated with the access request to the logic controller through the bus under the condition that the control right is detected to belong to the processor.
6. 6. The apparatus of claim 5, wherein the application module comprises a plurality of software application layers, a plurality of third party software call interfaces and a plurality of platform interface conversion layers, wherein the plurality of software application layers are in one-to-one correspondence with the plurality of third party software call interfaces, and the plurality of third party software call interfaces are in one-to-one correspondence with the plurality of platform interface conversion layers; The software application layer is used for receiving the access request and transmitting the access request to the corresponding platform interface conversion layer through the corresponding third-party software calling interface; the platform interface conversion layer is used for modifying the bottom read-write access into a bus access mode and transmitting the access request to the bus read-write drive based on the bus access mode.
7. 7. The device according to any one of claims 1-4, wherein the logic controller further comprises a plurality of interface read-write modules and a bus read-write module, wherein each interface read-write module is correspondingly connected with each actuator, the space storage area comprises a plurality of storage blocks, the storage blocks are in one-to-one correspondence with the plurality of interface read-write modules, and the bus read-write modules are connected with the processor through the bus; the bus read-write module is used for receiving data associated with the access request and writing the data into the space storage area; And the interface read-write module is used for detecting the control right of the space storage area according to the second space owner information, and reading data from the space storage area and performing data access on an actuator to be accessed by the access request under the condition that the control right belongs to the logic controller.
8. 8. A parallel access method, characterized in that the parallel access method is applied to a processor in a parallel access apparatus according to any of claims 1-7, the method comprising: Detecting the control right of the space storage area according to the first space owner information stored in the target memory of the processor when an access request is received; and under the condition that the control right belongs to the processor, performing data access with an executor to be accessed by the access request through the logic controller.
9. 9. The method of claim 8, wherein the method further comprises: when the logic controller releases the control right of the logic controller, a first owner zone bit in the first space owner information is modified from a second numerical value to a first numerical value, wherein the first numerical value indicates that the control right belongs to the processor, and the second numerical value indicates that the control right belongs to the logic controller.
10. 10. The method of claim 8, wherein detecting control of a spatial storage area based on first spatial owner information stored in a target memory of the processor comprises: Inquiring a first owner zone bit in the first space owner information; If the first owner zone bit is a first numerical value, determining that the control right of the space storage area belongs to the processor; and if the first owner zone bit is a second value, determining that the control right of the space storage area belongs to the logic controller.
11. 11. The method of claim 8, wherein the accessing, by the logic controller, data with an actuator to which the access request is to be accessed, comprises: Acquiring information associated with the access request, wherein the information comprises read information or write information; Transmitting information associated with the access request to the logic controller through the bus, and releasing the control right of the processor to the logic controller according to the first space owner information, wherein the information is used for indicating the logic controller to perform data access with an executor to be accessed by the access request.
12. 12. The method of claim 11, wherein releasing control of the processor to the logic controller based on the first spatial owner information comprises: And modifying the first owner zone bit in the first space owner information from a first value to a second value.
13. 13. A parallel access method, characterized in that the parallel access method is applied to a logic controller in a parallel access apparatus according to any one of claims 1-7, the method comprising: detecting the control right of the space storage area according to the second space owner information; and under the condition that the control right belongs to the logic controller, performing data access with an executor to be accessed by the access request.
14. 14. The method of claim 13, wherein the method further comprises: When a processor in the parallel access device releases the control right of the processor, a second owner zone bit in the second space owner information is modified from a first value to a second value, wherein the first value indicates that the control right belongs to the processor, and the second value indicates that the control right belongs to the logic controller.
15. 15. The method of claim 13, wherein detecting control of a spatial storage area based on the second spatial owner information comprises: inquiring a second owner zone bit in the second space owner information; If the second owner zone bit is the first value, determining that the control right of the space storage area belongs to the processor; and if the second owner flag bit is a second value, determining that the control right of the space storage area belongs to the logic controller.
16. 16. The method of claim 13, wherein the accessing data with the executor to which the access request is to access comprises: If the access request is a read request, acquiring a read address and a read instruction according to information associated with the access request stored in the space storage area, and reading data from a corresponding executor according to the read address and the read instruction; And if the access request is a write request, acquiring a write address, a write instruction and write data according to information related to the access request stored in the space storage area, and writing the write data into a corresponding executor according to the write address and the write instruction.
17. 17. The method of claim 16, wherein after the reading of data from the corresponding actuator according to the read address and the read instruction, the method further comprises: And transmitting the read data to the space storage area, and releasing the control right of the logic controller to the processor according to the second space owner information.
18. 18. The method of claim 17, wherein releasing control of the logical controller to the processor based on the second spatial owner information comprises: and modifying a second owner flag bit in the second space owner information from a second numerical value to a first numerical value.
19. 19. An antenna component system, characterized by a parallel access arrangement according to any of claims 1-7 for performing a parallel access method according to any of claims 5-18.
20. 20. A parallel access device, comprising a memory, a transceiver, and a processor: the system comprises a memory for storing a computer program, a transceiver for receiving and transmitting data under the control of the processor, and a processor for reading the computer program in the memory and performing the following operations: Detecting the control right of the space storage area according to the first space owner information stored in the target memory of the processor when an access request is received; and under the condition that the control right belongs to the processor, performing data access with an actuator to be accessed by the access request through a logic controller.

Description

Parallel access device, parallel access method, antenna component system, storage medium, and program product Technical Field The present application relates to the field of antenna technology, and in particular, to a parallel access device, a parallel access method, an antenna assembly system, a storage medium, and a program product. Background A radio frequency analog transceiver (RF TRANSCEIVER, TRX) and a beam forming chip (BF) are used as core devices of the 5G base station, and the data transmission efficiency between the radio frequency analog transceiver and a processor in the antenna array assembly system directly affects the signal transceiving performance of the antenna array on the 5G base station. In the related art, control management of a TRX or BF chip is typically implemented by selectively using a programmable array logic device (Field Programmable GATE ARRAY, FPGA) to extend a high-speed full-duplex synchronous serial communication technology (SERIAL PERIPHERAL INTERFACE, SPI) interface within an antenna array assembly system. Moreover, when the number of TRX or BF chips is large, parallel access at the same time can be realized through a plurality of extended SPI interfaces. However, the related art method in which processors access TRX or BF chips in parallel has a problem of low access efficiency. Disclosure of Invention In view of the foregoing, it is desirable to provide a parallel access apparatus, a parallel access method, an antenna assembly system, a storage medium, and a program product that can improve the parallel access efficiency. The application provides a parallel access device, which comprises a processor, a logic controller and a plurality of executors, wherein the processor is connected with the logic controller through a bus; the processor is internally provided with a target memory, and first space owner information is stored in the target memory; a space storage area is arranged in the logic controller, and second space owner information is stored in the space storage area; The processor is used for detecting the control right of the space storage area according to the first space owner information when an access request is received, and carrying out data transmission with the logic controller through the bus under the condition that the control right is detected to belong to the processor; And the logic controller is used for detecting the control right of the space storage area according to the second space owner information, and performing data access with an executor to be accessed by the access request under the condition that the control right belongs to the logic controller. In one embodiment, the processor is further configured to release, after data transmission with the logic controller through the bus, control rights of the processor to the logic controller according to the first space owner information; the logic controller is further used for releasing the control right of the logic controller to the processor according to the second space owner information after the logic controller performs data access with the executor to be accessed by the access request. In one embodiment, when the processor releases the control right of the processor to the logic controller according to the first spatial owner information, the processor is specifically configured to modify a first owner flag bit in the first spatial owner information from a first value to a second value; correspondingly, when the processor releases the control right of the processor, the logic controller is further configured to modify a second owner flag bit in the second spatial owner information from the first value to the second value, where the first value indicates that the control right belongs to the processor, and the second value indicates that the control right belongs to the logic controller. In one embodiment, when the control right of the logic controller is released to the processor according to the second spatial owner information, the logic controller is specifically configured to modify a second owner flag bit in the second spatial owner information from a second value to a first value; correspondingly, the processor is further configured to modify a first owner flag bit in the first spatial owner information from the second value to the first value when the logic controller releases the control right of the logic controller. In one embodiment, the processor further comprises a bus read-write driver and a plurality of application modules; the application module is used for receiving the access request and transmitting the access request to the bus read-write driver; The bus read-write driver is used for detecting the control right of the space storage area according to the first space owner information, and transmitting the data associated with the access request to the logic controller through the bus under the condition that the control right is detected to belong to the process