CN-121996610-A - AI processor based on integrative, three-dimensional integration and JEDEC interface of deposit

Abstract

The application relates to an AI processor based on a memory integration, three-dimensional integration and JEDEC interface, at least one storage unit configured to store input characteristic data, neural network weight data, characteristic data and intermediate calculation results of an input neural network model, at least one calculation unit communicatively coupled with the at least one storage unit through a three-dimensional integration technology, the calculation unit comprising a neural network processing unit based on a memory integration array and configured to perform neural network related calculation by using data of the storage unit, and at least one JEDEC interface device arranged on the storage unit or the calculation unit, at least compatible with one JEDEC memory standard protocol and configured to be capable of controlling operation of the calculation unit based on external instructions. The functional limitation of the traditional interface device is broken through, and the problems of low computational intensity, limited bandwidth and poor interface universality of the traditional neural network processor are solved.

Inventors

• WANG ZHIXUAN
• YE LE
• CHEN PEIYU
• LIU YING

Assignees

• 无锡微纳核芯电子科技有限公司
• 杭州微纳核芯电子科技有限公司

Dates

Publication Date

20260508

Application Date

20260202

Claims (20)

1. 1. An AI processor based on a memory-accounting integration, three-dimensional integration and JEDEC interface, comprising: At least one storage unit configured to store input feature data, neural network weight data, feature data, intermediate calculation results of the input neural network model; at least one computing unit communicatively coupled to the at least one memory unit by a three-dimensional integration technique, the computing unit including a memory-integrated-array-based neural network processing unit configured to perform neural network-related computations using data of the memory unit, and At least one JEDEC interface device, disposed in the storage unit or the computing unit, compatible with at least one JEDEC memory standard protocol, and configured to control operation of the computing unit based on external instructions.
2. 2. The memory integrated, three-dimensional integrated and JEDEC interface-based AI processor of claim 1, wherein said JEDEC interface means comprises: a JEDEC interface circuit for receiving the external instruction including at least one of data, address, or JEDEC instruction, and And the JEDEC protocol analyzer is connected with the JEDEC interface circuit and can analyze the data and/or the address into a control signal which can be identified by the storage unit and send the control signal to the storage circuit of the storage unit.
3. 3. The memory integrated, three-dimensional integrated and JEDEC interface-based AI processor of claim 2, wherein the computing unit includes a computing unit instruction parser, coupled to the JEDEC interface circuitry, capable of remapping the JEDEC instructions to computing instructions recognizable by the computing unit.
4. 4. The memory-integrated, three-dimensional integrated, JEDEC interface-based AI processor of claim 2, wherein the computing unit includes a computing unit instruction parser, coupled to the memory circuit, capable of mapping data written to the memory circuit specific address space into computing instructions recognizable by the computing unit.
5. 5. The memory, three-dimensional integration, and JEDEC interface-based AI processor of claim 1, wherein said JEDEC interface means is configured to: receiving a storage unit access instruction of an external main control chip; after the external instruction is analyzed, the computing unit is controlled to execute neural network operation, or the storage unit is controlled to execute data read-write; Multiplexing of the storage instruction and the calculation instruction is achieved based on a preset protocol remapping mechanism.
6. 6. The memory-integrated, three-dimensional integrated, and JEDEC interface-based AI processor of claim 5, the protocol remapping mechanism comprising: and mapping first storage data into a computing instruction which can be identified by the computing unit, wherein the first storage data is the storage data read and written to a storage circuit of a specific address space of the storage unit.
7. 7. The memory-integrated, three-dimensional integrated, and JEDEC interface-based AI processor of claim 5, the protocol remapping mechanism comprising: A reserved field is defined in the standard JEDEC instruction set as a calculation instruction that the calculation unit can recognize, or, And (3) part of instructions of the standard JEDEC instruction set are repeatedly utilized, and the part of instructions are synchronized to be used as computing instructions which can be identified by the computing unit.
8. 8. The memory integrated, three-dimensional integrated, and JEDEC interface-based AI processor of claim 7, wherein said "recycling partial instructions of the standard JEDEC instruction set" includes a mode register write command utilizing the JEDEC standard, The JEDEC interface device is used for: mapping the exclusive instruction register address of the computing unit to a reserved area of a JEDEC mode register address space; When the JEDEC interface device detects a command written in a register with a target address of the reserved area, instruction parameter data carried by the command are distributed to a corresponding calculation type register, parameter configuration register or address register so as to trigger the operation of the calculation unit.
9. 9. The AI processor of claim 7 wherein defining a reserved field in a standard JEDEC instruction set as a computation instruction recognizable by the computation unit includes multiplexing computation instructions with storage instructions using transmission cycles and extension bits of a command/address bus; the JEDEC interface device is used for: monitoring signal combination of command/address bus, when detecting that command/address bus signal is in extended command period and contains specific extended bit state and undefined signal combination, identifying it as exclusive instruction identification of AI processor; And according to the exclusive instruction identification, analyzing the data in the data period of the subsequent transmission into instruction parameters for driving the calculation unit to calculate.
10. 10. The memory-integrated, three-dimensional integrated, and JEDEC interface-based AI processor of claim 6, wherein said "specific address space" is a reserved unoccupied area declared by a base address register in the JEDEC specification; the JEDEC interface device is used for: Dividing the specific address space into at least two functional subsections, wherein a first subsection is used for mapping calculation class instructions, and a second subsection is used for mapping configuration class instructions; Triggering a matrix operation or a convolution operation when a write operation to the first sub-segment is detected; when a write operation to the second sub-segment is detected, a calculation accuracy configuration or an abnormal reset operation is performed.
11. 11. The memory, three-dimensional integration, and JEDEC interface-based AI processor of any of claims 1-10, wherein the memory array-based neural network processing unit is configured to: receiving input characteristic data of a neural network and weight data from the storage unit; performing a neural network calculation based on the weight data and the input feature data, and And outputting the calculation result to the storage unit or the external equipment.
12. 12. An AI processor based on a memory integration, three-dimensional integration and JEDEC interface according to any of claims 1-10, wherein said JEDEC interface means is compatible with JEDEC memory standard protocols, capable of being recognized as a standard memory device and accessed in memory format by a host system or a memory controller supporting the JEDEC standard.
13. 13. The memory integrated, three-dimensional integrated and JEDEC interface-based AI processor of any one of claims 1-10, wherein the three-dimensional integrated technology includes at least one of through silicon via technology, flip chip technology, hybrid bonding technology, micro bump connection technology.
14. 14. An AI processor based on a memory, three-dimensional integration and JEDEC interface according to any of claims 1-10 and wherein JEDEC memory standard protocols supported by said JEDEC interface means are selected from at least one of DDR4、DDR5、DDR6、LPDDR4、LPDDR4X、LPDDR5、LPDDR5X、LPDDR5T、LPDDR6、LPDDR6X、LPDDR6T、HBM2、HBM3、HBM4、HBM5、GDDR5、GDDR6、GDDR7、UFS、eMMC .
15. 15. The memory, three-dimensional integrated and JEDEC interface based AI processor of any one of claims 1-10, wherein the memory unit and the computing unit are capable of interchanging stacking order to accommodate different heat dissipation and stress requirements.
16. 16. The memory, three-dimensional integration, and JEDEC interface-based AI processor of any of claims 1-10, further comprising: an interface checking circuit for performing error detection and correction on the command and data information interacted with the external main control chip by the JEDEC interface device to prevent error data from entering the memory unit or the computing unit, and And the on-chip checking circuit is used for carrying out error detection and correction on the data stored in the storage unit and the intermediate calculation result in the calculation unit so as to ensure the reliability of the data in the AI processor in the cross-layer transmission and calculation process.
17. 17. The memory integrated, three-dimensional integrated and JEDEC interface-based AI processor of claim 16, wherein said interface verification circuitry and on-chip verification circuitry are disposed in said memory unit if said JEDEC interface device is disposed in said memory unit.
18. 18. The memory integrated, three-dimensional integrated and JEDEC interface-based AI processor of claim 16, wherein if said JEDEC interface device is disposed at said computing unit, said interface verification circuitry is disposed at said computing unit and said on-chip verification circuitry is disposed at said memory unit or at said computing unit or at said memory unit.
19. 19. The AI processor of any of claims 1-10, based on a computational integration, three-dimensional integration, and JEDEC interface, the computational integration array implemented based on at least one of SRAM, reRAM, MRAM or FeFET technologies.
20. 20. The AI processor of any of claims 1-10, wherein the JEDEC interface device is configured with arbitration means for processing received instructions and data when the computing unit accesses the memory unit, the arbitration mechanism of the arbitration means including masking, receiving, partially receiving the external instructions or data.

Description

AI processor based on integrative, three-dimensional integration and JEDEC interface of deposit Technical Field The application relates to the technical field of artificial intelligence, in particular to an AI processor based on a memory-accounting integration, three-dimensional integration and JEDEC interface. Background Currently, two types of interfaces, PCIe (Peripheral Component Interconnect Express) interfaces or custom interfaces, are mainly used for communication between the neural network processor and the host system. PCIe provides a high bandwidth (e.g., PCIe 7.0 up to 512 GB/s) for a high speed serial computer expansion bus standard, but itself also introduces significant power consumption and delay overhead, which may be a new bottleneck at the system level. More importantly, PCIe interfaces are not available in all computing platforms, especially in mobile and edge computing scenarios such as cell phones, internet of things devices, and the like. While the adoption of the custom interface can be optimized for specific applications, serious ecological fragmentation is caused, flexibility of hardware selection is limited, and complexity and cost of system integration are increased. In summary, the standard interface solves the connectivity, but is itself a bottleneck or inadequately applicable, and thus, improvements to existing neural network processors are needed. Disclosure of Invention In view of the above problems, the present application provides an AI processor (i.e., a neural network processor) based on a memory integrated, three-dimensional integrated and JEDEC interface, comprising at least one storage unit configured to store input feature data, neural network weight data, feature data, intermediate calculation results of an input neural network model, at least one calculation unit communicatively coupled to the at least one storage unit through a three-dimensional integration technique, the calculation unit comprising a memory integrated array-based neural network processing unit configured to perform neural network-related calculations using data of the storage unit, and at least one JEDEC (solid state technology association) interface device provided to the storage unit or the calculation unit, at least compatible with one JEDEC memory standard protocol, and configured to be capable of controlling operations of the calculation unit based on external instructions. In addition, the JEDEC interface device is configured to control the operation of the computing unit, compared with the JEDEC interface device in the prior art, only controls the storage unit, thereby breaking through the functional limitation of the traditional interface device and improving the universality of the interface. Optionally, the JEDEC interface device comprises a JEDEC interface circuit for receiving an external instruction, wherein the instruction comprises at least one of data, an address and a JEDEC instruction, and a JEDEC protocol parser connected with the JEDEC interface circuit and capable of parsing the data and the address into control signals which can be identified by the storage unit and sending the control signals to the storage circuit of the storage unit. The application adds a protocol analysis function in the JEDEC interface device, so that the external standard storage access instruction can be analyzed into the internal identifiable control signal of the processor, and the protocol compatibility and seamless interaction between the external main control and the self-research architecture are realized. Optionally, the computing unit includes a computing unit instruction parser, connected to the JEDEC interface circuit, capable of remapping JEDEC instructions into computing instructions recognizable by the computing unit. According to the application, the instruction analyzer is arranged at the side of the computing unit, and JEDEC standard instructions are remapped into computing control instructions, so that a master control can directly issue computing tasks without additional custom interfaces, the universality of the interfaces is improved, and the complexity of system development is reduced. Optionally, the computing unit includes a computing unit instruction parser, coupled to the memory circuit, capable of mapping data written to the memory circuit specific address space into computing instructions recognizable by the computing unit. The application can automatically trigger the corresponding calculation instruction by the data access of the specific address space through the predefined address mapping mechanism, realize the multiplexing and the rapid scheduling of the instruction level, and further reduce the control delay. Optionally, the JEDEC interface device is configured to: receiving a storage unit access instruction of an external main control chip; after analyzing the instruction, controlling the computing unit to execute neural network operation or controlling the data readi