CN-121996612-A - Computer driving system for communication satellite service

CN121996612ACN 121996612 ACN121996612 ACN 121996612ACN-121996612-A

Abstract

The invention relates to a computer driving system for a communication satellite, which comprises a CPU processor, a first FPGA chip and a second FPGA chip, wherein the first FPGA chip comprises a first communication subsystem, a first state acquisition subsystem, a first power distribution control subsystem, an analog acquisition subsystem, a gesture control subsystem and a time management subsystem, the first state acquisition subsystem, the first power distribution control subsystem, the analog acquisition subsystem, the gesture control subsystem and the time management subsystem conduct data interaction with the CPU processor through the first communication subsystem, the second FPGA chip comprises a second communication subsystem, a second state acquisition subsystem, an interrupt subsystem, an interface subsystem, a second power distribution control subsystem and a storage subsystem, and the second state acquisition subsystem, the interrupt subsystem, the interface subsystem, the second power distribution control subsystem and the storage subsystem conduct data interaction with the CPU processor through the second communication subsystem.

Inventors

ZHANG CHENSHUO
YANG PEI
SONG YIFAN
ZHANG YADONG
MA YANLIANG

Assignees

上海格思航天科技有限公司

Dates

Publication Date: 20260508
Application Date: 20260211

Claims (10)

1. The computer driving system for the communication satellite service is characterized by comprising a CPU processor (1), a first FPGA chip (2) and a second FPGA chip (3); The first FPGA chip (2) comprises a first communication subsystem (21), a first state acquisition subsystem (22), a first power distribution control subsystem (23), an analog acquisition subsystem (24), a gesture control subsystem (25) and a time management subsystem (26); The first state acquisition subsystem (22), the first power distribution control subsystem (23), the analog acquisition subsystem (24), the attitude control subsystem (25) and the time management subsystem (26) perform data interaction with the CPU processor (1) through the first communication subsystem (21); the second FPGA chip (3) comprises a second communication subsystem (31), a second state acquisition subsystem (32), an interruption subsystem (33), an interface subsystem (34), a second power distribution control subsystem (35) and a storage subsystem (36); The second state acquisition subsystem (32), the interrupt subsystem (33), the interface subsystem (34), the second power distribution control subsystem (35) and the storage subsystem (36) perform data interaction with the CPU processor (1) through the second communication subsystem (31).
2. The computer-driven system for communication satellite according to claim 1, wherein the first communication subsystem (21) and the second communication subsystem (31) are used for controlling a single satellite to realize control management functions of satellite management, attitude control, measurement and control communication and payload tasks, the first state acquisition subsystem (22) and the second state acquisition subsystem (32) are used for acquiring satellite state signals, the first distribution control subsystem (23) and the second distribution control subsystem (35) are used for powering up and down each single satellite, the analog acquisition subsystem (24) is used for detecting the power-up and power-down state of each single satellite, the attitude control subsystem (25) is used for controlling a magnetic torquer, and the time management subsystem (26) is used for timing and timing the satellite and providing a time reference.
3. The computer driving system for the communication satellite according to claim 1, wherein the first communication subsystem (21) and the second communication subsystem (31) comprise an EMIF bus module (211), the EMIF bus module (211) distinguishes two FPGAs through different chip selection signals, and the two FPGAs realize data interaction between the CPU and each module of the FPGA through address partitioning.
4. The computer-driven system for communicating satellites according to claim 1, wherein the first state acquisition subsystem (22) and the second state acquisition subsystem (32) each comprise a sailboard signal acquisition module (221), a satellite-arrow separation signal acquisition module (222), a current acquisition module (223), and a temperature acquisition module (224); The system comprises a sailboard signal acquisition module (221) and a satellite rocket separation signal acquisition module (222), wherein the sailboard signal acquisition module (221) is used for monitoring the unfolding state of a communication satellite sailboard, the satellite rocket separation signal acquisition module (222) is used for monitoring the separation state of a satellite and a carrier rocket, the current acquisition module (223) is used for controlling an INA3221 chip to realize the acquisition of 32 paths of current flows through an IIC bus, and the temperature acquisition module (224) is used for monitoring the temperature condition of each part inside the satellite in real time.
5. The computer-driven system for communication satellite according to claim 1, wherein the first power distribution control subsystem (23) and the second power distribution control subsystem (35) each comprise an IO control module (231) and a verification module (232), and the IO control module (231) analyzes the EMIF bus data subjected to CRC verification by the verification module (232) to analyze the IO state of the corresponding FPGA to control, so as to implement power-on/power-off operation.
6. The computer-driven system for communication satellite according to claim 1, wherein the analog quantity acquisition subsystem (24) comprises an ADC module (241) and a time-sharing driving module (242), the ADC module (241) is configured to acquire analog quantity data by controlling an AD1674 chip, and the time-sharing driving module (242) is configured to perform ping-pong storage on the data acquired by the ADC module (241).
7. The computer-driven system for communicating satellites according to claim 1, wherein the attitude control subsystem (25) comprises a magnetic torquer module (251) for effecting attitude control of satellites.
8. The computer-driven system for communicating satellites as claimed in claim 1, wherein the time management subsystem (26) comprises a time service module (261), a centralized timing module (262), a uniform timing module (263), a PPS module (264) and a clock calibration module (265), and is used for synchronizing, calibrating and managing the time of the satellite system, and ensuring the time consistency and accuracy between the subsystems in the satellite system.
9. The computer-driven system for communication satellite according to claim 1, wherein the interrupt subsystem (33) comprises an interrupt management module (331), the interrupt management module (331) triggering a CPU interrupt by an output falling edge, controlling interrupt priority by IO sequencing of the corresponding FPGA.
10. The computer-driven system for communicating satellites according to claim 1 wherein the interface subsystem (34) comprises an RS422 module (341) and CAN IP module (342) and a remote telemetry module (343), and the storage subsystem (36) comprises an SRAM module (361) and a norflast module (362).

Description

Computer driving system for communication satellite service Technical Field The invention relates to the technical field of satellite service computer driving, in particular to a satellite service computer driving system for communication. Background Communication satellite service computer drive designs are closely related to communication satellite service computer architecture, which is evolving from decentralized to centralized. Each subsystem (power supply, thermal control and gesture) of the early distributed architecture has an independent controller, and is connected through a point-to-point or simple bus, so that the early distributed architecture has the advantages of simple driving design of each module, no diffusion of local faults, complex driving configuration items and weak coordination capability. At present, a main flow star computer architecture is a centralized architecture, one star computer with strong functions is responsible for management and data processing of all platform subsystems, the star computer usually adopts a single-chip SOC architecture or a single-chip CPU+single-chip FPGA architecture, and the architecture is limited by the problems of limited hardware resources, poor function expansibility, low communication rate and the like. Because conventional processor architectures limit the speed and efficiency of data processing and signal processing, they often present performance bottlenecks and limitations in coping with insufficient capacity in the face of rapidly iterated communication satellite tasks. Therefore, a novel driving design scheme is urgently needed, and the comprehensive support for function expansion can be realized while high performance, high reliability, high integration and low cost are met, so that the performance and reliability of the communication satellite service system are improved. The foregoing description is provided for general background information and does not necessarily constitute prior art. Disclosure of Invention The invention aims to provide a communication satellite service computer driving system, which improves the overall performance, integration level and expansibility of a satellite system, realizes the comprehensive support and management of functions of various aspects of a communication satellite, and meets the diversified requirements of the satellite under different task scenes. The invention provides a computer driving system for a communication satellite, which comprises a CPU processor, a first FPGA chip and a second FPGA chip, wherein the first FPGA chip comprises a first communication subsystem, a first state acquisition subsystem, a first power distribution control subsystem, an analog acquisition subsystem, a gesture control subsystem and a time management subsystem, the first state acquisition subsystem, the first power distribution control subsystem, the analog acquisition subsystem, the gesture control subsystem and the time management subsystem interact data with the CPU processor through the first communication subsystem, and the second FPGA chip comprises a second communication subsystem, a second state acquisition subsystem, an interrupt subsystem, an interface subsystem, a second power distribution control subsystem and a storage subsystem, and the second state acquisition subsystem, the interrupt subsystem, the interface subsystem, the second power distribution control subsystem and the storage subsystem interact data with the CPU processor through the second communication subsystem. Further, the first communication subsystem and the second communication subsystem are used for controlling a single satellite unit to realize control management functions of satellite management, attitude control, measurement and control communication and payload tasks, the first state acquisition subsystem and the second state acquisition subsystem are used for acquiring satellite state signals, the first power distribution control subsystem and the second power distribution control subsystem are used for powering on and off each single satellite unit, the analog quantity acquisition subsystem is used for detecting the power-on and power-off states of each single satellite unit, the attitude control subsystem is used for controlling a magnetic torquer, and the time management subsystem is used for timing and providing a time reference for the satellite. The first communication subsystem and the second communication subsystem respectively comprise an EMIF bus module, the EMIF bus module distinguishes two FPGAs through different chip selection signals, and the two FPGAs realize data interaction between the CPU and each module of the FPGAs through address partitioning. Further, the first state acquisition subsystem and the second state acquisition subsystem respectively comprise a sailboard signal acquisition module, a satellite and arrow separation signal acquisition module, a current acquisition module and a temperature acquisitio