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CN-121996613-A - Multi-time-scale parallel interactive simulation method and system suitable for self-adaptive converter

CN121996613ACN 121996613 ACN121996613 ACN 121996613ACN-121996613-A

Abstract

Aiming at the problem that the real-time performance and the precision are difficult to be considered in the traditional single simulation step size due to the multi-time-scale dynamic mode of the self-adaptive converter, the invention constructs a CPU-FPGA heterogeneous simulation framework, namely a rectification side model, a direct current side model, an inversion side model, an LCC model and a control system model are deployed on the CPU side, an SVG model is deployed on the FPGA side, a multi-rate decoupling algorithm is adopted for solving the problem of strong coupling caused by different step size interaction, a strong coupling branch is decomposed into two Thevenin equivalent subcircuits which can be independently calculated through historical electrical quantity data at an interface based on an inductance discretization model, the parallel interactive calculation of a fast-slow time scale model is effectively realized, the precision bottleneck caused by the difference of simulation step sizes is overcome, and the full-working condition high-efficiency and high-precision real-time simulation of the self-adaptive converter system is realized.

Inventors

  • XU XIAN
  • BI MINGDE
  • LI XIAO
  • CAO YI

Assignees

  • 国网江苏省电力有限公司

Dates

Publication Date
20260508
Application Date
20260410

Claims (10)

  1. 1. The multi-time-scale parallel interactive simulation method suitable for the adaptive converter is characterized by comprising the following steps of: Constructing a heterogeneous computation architecture based on a CPU and an FPGA, namely dividing a simulation model of the self-adaptive converter into a CPU side simulator and an FPGA side simulator according to the dynamic response characteristic of the component, wherein the simulation step length of the CPU side simulator is larger than that of the FPGA side simulator; The multi-rate decoupling algorithm is used for decoupling a connecting branch between a component deployed on the CPU side and a component deployed on the FPGA side, the multi-rate decoupling algorithm is based on an inductance discretization model, the connecting branch is decomposed into two Thevenin equivalent subcircuits which are independently calculated through history items, so that the simulation machines on the CPU side and the FPGA side independently operate based on the optimal simulation step length, boundary data interaction is carried out through a communication interface, and each model and each control system deployed on the CPU side and the FPGA side are updated in parallel according to the calculation result of the Thevenin equivalent subcircuits.
  2. 2. The multi-time scale parallel interactive simulation method according to claim 1, wherein the multi-rate decoupling algorithm based on the inductance discretization model specifically comprises: discretizing an inductance continuous model shown in the formula (1) by adopting a trapezoidal integral rule: wherein u k (t) and u m (t) represent node instantaneous voltages, i L (t) represent branch currents, and in order to ensure high value fidelity of the linear passive network, a trapezoidal integration rule is adopted, and equation (1) is applied to the time step Internal integration to obtain: let the equivalent characteristic resistance be defined as For simplifying the symbol, superscript "is used" "Means the previous time step ) Substituting the above definition into (3) and sorting each term to express the inductance voltage Further, a davienan equivalent model is obtained: Equation (3) shows that the voltage drop depends on the instantaneous current and the history, and to achieve a decoupling interface, equation (4) is further developed into a symmetrical form: The equation (4) clarifies the core principle of the discrete division method of the inductance, the inductance model is conveniently divided into two symmetrical sub-circuits by using a delay element and a controlled voltage source, and the mathematical structure can realize decoupling of the global system matrix at an inductance port.
  3. 3. The multi-time scale parallel interactive simulation method according to claim 2, wherein the maximum relative amplitude error of the multi-rate decoupling algorithm in the frequency range of 0-5000 Hz is not more than 3.3%, and the CPU side time step used for discretization is 20 μs.
  4. 4. A simulation system for implementing the multi-time scale parallel interactive simulation method according to any one of claims 1 to 3, comprising: a CPU side simulator configured to perform simulation calculation of the CPU side part; the FPGA side simulator is configured to execute simulation calculation of the FPGA side component; And the high-speed communication module is connected with the simulator at the FPGA side and the simulator at the CPU side and is configured for realizing data interaction at two sides.
  5. 5. The simulation system of claim 4, wherein the CPU side simulator is configured with a rectification side model, a DC side model, an inversion side model, an LCC rectification side control system, an LCC inversion side control system, and an SVG control system, and wherein the FPGA side simulator is configured with an SVG model.
  6. 6. The simulation system of claim 5, wherein the communication interface of the high-speed communication module is an optical fiber communication interface for transmitting the commutation voltage and the dc current critical electrical quantity to reduce communication delay and electromagnetic interference.
  7. 7. A simulation model for realizing the multi-time-scale parallel interaction simulation method according to any one of claims 1-3 is characterized by comprising a simulation machine deployed on a CPU side, a simulation machine deployed on an FPGA side and a communication interface for connecting the CPU side and the FPGA side simulation machine, wherein the CPU side simulation machine comprises a rectification side model, a direct current side model, an inversion side model, an LCC rectification side control system, an LCC inversion side control system and an SVG control system, the FPGA side simulation machine comprises an SVG model, and the simulation step length of the CPU side simulation machine is longer than that of the FPGA side simulation machine; The system comprises a rectification side model, a direct current side model, an inversion side model, an LCC (inductance capacitance) rectification side control system, an LCC inversion side control system and an SVG (static var generator) model, wherein the rectification side model, the direct current side model and the inversion side model are sequentially connected, the LCC model is connected with the rectification side model and the inversion side model, the SVG model is connected with the rectification side model, the rectification side model is used for converting alternating current into direct current and providing electric quantity, the direct current side model is used for transmitting the direct current electric quantity, the inversion side model is used for converting direct current into alternating current and providing electric quantity, the LCC model and the SVG model are used for outputting the electric quantity and updating according to corresponding control instructions, electric quantity interaction is carried out at a connecting branch, and one simulation period of a simulation system is completed, the LCC rectification side control system is connected with the rectification side model, the LCC inversion side control system is connected with the inversion side model, the LCC inversion side control system is connected with the LCC model, and the SVG control system is connected with the SVG model.
  8. 8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the multi-time scale parallel interactive simulation method of any of claims 1-3 when executing the computer program.
  9. 9. A computer readable storage medium having stored thereon a computer program, wherein the computer program, when executed by a processor, implements the multi-time scale parallel interactive simulation method of any of claims 1-3.
  10. 10. The multi-time scale parallel interactive simulation method suitable for the self-adaptive converter is characterized by being applied to simulation verification work of a new power electronic topology and being suitable for various laboratory environments.

Description

Multi-time-scale parallel interactive simulation method and system suitable for self-adaptive converter Technical Field The invention belongs to the technical field of electromagnetic transient simulation of a high-voltage direct-current transmission system, relates to a multi-time-scale parallel interactive simulation method and system suitable for a self-adaptive converter, and particularly relates to a simulation model suitable for the self-adaptive converter and a simulation method and system thereof. Background Along with the rapid development of high-proportion access of new energy power generation to a power grid and an alternating current/direct current hybrid power grid, the dynamic characteristics of a power system are increasingly complex, and higher requirements are put on the precision and efficiency of a simulation technology. Under the background, a novel commutation technology such as a self-adaptive commutation converter (self-commutated converter, SLCC) of a fully-controlled power electronic device is adopted, and the self-adaptive commutation converter has become an important direction for upgrading a high-voltage direct-current transmission technology. The self-adaptive phase-change converter comprises a line-commutated converter (LCC) and a static var generator (STATIC VAR generator, SVG), wherein SVG is used as a reactive power and harmonic compensation component, and has a coupling relation with the LCC, so that engineering problems such as reactive power compensation, harmonic suppression, fault transient response and the like are brought. . At present, electromagnetic transient simulation of a power system is mainly based on a pure Central Processing Unit (CPU) architecture. However, when facing the simulation requirement of SVG high-frequency dynamic process (such as microsecond control period) in SLCC system, the prior art has the obvious defects that firstly, the serial calculation mode of CPU is difficult to meet the real-time requirement, so that the simulation speed cannot keep up with the dynamic response of the actual system, secondly, the simulation precision is difficult to match with the strict requirements of engineering application on harmonic analysis and transient characteristic research, thirdly, the special simulation model aiming at SLCC and other novel topologies is still immature, and the optimization of the control protection strategy and the deep analysis of the fault characteristic cannot be accurately supported. Therefore, an innovative simulation solution is needed to be constructed in the art, so that the novel converter technology such as SLCC can be effectively adapted, and the simulation efficiency is obviously improved on the premise of ensuring the simulation precision. According to the invention, a field-programmable gate array (FPGA) is introduced as a hardware acceleration core, so that a CPU+FPGA heterogeneous computing architecture is constructed and a multi-rate decoupling algorithm is combined. The FPGA can provide microsecond-level precision real-time simulation for the high-frequency dynamic process of SVG by means of the hardware parallel computing capability and the programmable characteristic, and effectively makes up the defects of the pure CPU architecture in real-time performance and precision. Disclosure of Invention In view of the above, the invention provides a multi-time scale parallel interactive simulation method and system suitable for a self-adaptive converter, which aims to realize high-efficiency and high-precision simulation of all working conditions of an SLCC system and provide accurate and efficient simulation support for optimization of an SLCC system control protection strategy and analysis of fault characteristics, and aims to solve the problems that the existing pure CPU simulation is insufficient in real time in an SVG high-frequency control process, the novel topology adaptability of the SLCC is poor, and the fault transient simulation precision is difficult to match engineering requirements. In order to achieve the above purpose, the present invention provides the following technical solutions: the adaptive commutation converters include grid commutation converters (LCCs) and Static Var Generators (SVGs). A multi-time scale parallel interactive simulation method suitable for an adaptive converter comprises the following steps: Constructing a heterogeneous computation architecture based on a CPU and an FPGA, namely dividing a simulation model of the self-adaptive converter into a CPU side simulator and an FPGA side simulator according to the dynamic response characteristic of the component, wherein the simulation step length of the CPU side simulator is larger than that of the FPGA side simulator; The multi-rate decoupling algorithm is used for decoupling a connecting branch between a component deployed on the CPU side and a component deployed on the FPGA side, the multi-rate decoupling algorithm is based on an induct