CN-121996891-A - Resistance inductance parameter extraction method and device, computer equipment and storage medium

Abstract

The application discloses a method, a device, a computer device and a storage medium for extracting resistance and inductance parameters, which are based on a generalized centroid basic function conversion method, the global non-conformal grid supporting triangle and bilinear surfaces is compatible with fast algorithm configuration and preprocessing. The application can convert vector bit integral calculation of non-conformal surface grid into scalar bit integral calculation of monopole mode by generalizing centroid basic function conversion, and extract current direction information into sparse matrix at one time. By applying the method of the application, the obtained linear system core matrix can be directly used for rapid algorithm configuration, and meanwhile, the total non-conformal grid is adapted.

Inventors

• DAI WENLIANG
• JIANG LIGUO
• WANG MINGYU
• LIU PING

Assignees

• 芯和半导体科技（上海）股份有限公司

Dates

Publication Date

20260508

Application Date

20260120

Claims (10)

1. 1. The method for extracting the resistance inductance parameter is characterized by comprising the following steps of: Dividing the surface of the conductor into surface elements, wherein the surface elements are triangle and bilinear surface mixed surface elements; Constructing a sparse mapping matrix from a loop to the bin; Discrete conductor surface currents based on centroid basis functions; Mapping the current of the loop onto the bin based on the sparse mapping matrix; constructing a precondition matrix; accelerating matrix vector multiplication based on the bin configuration FMM algorithm; and (5) post-processing to obtain the resistance inductance parameter.
2. 2. The method of claim 1, wherein constructing a sparse mapping matrix of loops to the bins comprises: Obtaining a dough unit All current vectors above K is a bin The index of the upper side, i is the index of the bin; If loop l sweeps across edges k 1 and k 2 and the current vector Is the same as the current direction of the loop, the current vector If the direction of (2) is opposite to the loop current direction, then three sparse matrices are expressed as: , , ; wherein x, y, z represent the x-, y-, z-component of the current vector.
3. 3. The resistive-inductive parameter extraction method of claim 2, wherein said mapping the current of the loop onto the bins based on the sparse mapping matrix comprises: the linear equation system for solving the resistance inductance parameter by loop current analysis is converted into: ; Where P represents a bin-based scalar bit integration matrix, Representing the equivalent surface impedance of the substrate, Indicating the loop current is represented by the loop current, Representing the loop voltage, T representing the transpose of the matrix; ; Wherein, the , , 。
4. 4. The method of claim 1, wherein the partitioning forms a non-conformal grid, wherein the mapping the current of the loop onto the bins based on the sparse mapping matrix comprises: And mapping the loop current to the surface element based on the sparse mapping matrix, and extracting the current directivity to the matrix element at one time in the mapping process, so that the vector bit integration of the non-conformal grid is converted into the scalar bit integration of the monopole mode.
5. 5. The method of any one of claims 1-4, wherein the sparse mapping matrix Is of the dimension of , Indicating the number of loop currents, Representing the number of bins.
6. 6. The method of any one of claims 1-4, wherein the conductor surface is discrete by triangular and bilinear surfaces, and non-conformality is allowed between the grids.
7. 7. The method of any one of claims 1-4, wherein the sparse mapping matrix The non-zero element detection circuit comprises a non-zero element, wherein a row index of the non-zero element corresponds to a loop current number, and a column index of the non-zero element corresponds to a bin edge number; when the loop sweeps across two edges of a cell, the local current on one edge is made to base Local current base on the other side in the same direction as the loop current The direction is opposite to the loop current direction; The non-zero element is X, y, z components of (c).
8. 8. A resistive inductance parameter extraction device, comprising: the subdivision module is used for subdividing the surface of the conductor into surface elements, wherein the surface elements are triangle and bilinear surface mixed surface elements; a first construction module for constructing a sparse mapping matrix of loops to the bins; A discrete module for dispersing the conductor surface current based on the centroid basic function; a mapping module for mapping the current of the loop onto the bin based on the sparse mapping matrix; The second construction module is used for constructing a precondition matrix; the configuration module is used for configuring an FMM algorithm based on the surface elements to accelerate matrix vector multiplication; And the post-processing module is used for post-processing to obtain the resistance inductance parameter.
9. 9. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the resistive-inductive parameter extraction method according to any one of claims 1-7.
10. 10. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the resistive-inductive parameter extraction method of any of claims 1-7 when the program is executed by the processor.

Description

Resistance inductance parameter extraction method and device, computer equipment and storage medium Technical Field The application relates to a method, a device, computer equipment and a storage medium for extracting resistance and inductance parameters supporting global non-conformal grids, belonging to the field of algorithm optimization for parasitic parameter extraction. Background In power integrity analysis of advanced package (e.g., interposer) structures, the wiring layer typically includes an array of vias that are distributed throughout the globe. If electromagnetic simulation is performed using conventional conformal grid techniques, these dense vias divide the continuous metal layer structure into a large number of fragments, resulting in a large number of fine grids of poor quality in the vicinity of the vias. This not only increases the dimensions of the system matrix dramatically, but also severely degrades the behavior of the matrix, significantly reducing the convergence speed of solving the linear system and even resulting in solution failure. To address the challenges of non-conformal meshes, the prior art mainly employs a solution combined with a region decomposition method (Domain Decomposition Method, DDM) to implement a local non-conformal mesh. Common methods include: (1) The discontinuous Galerkin method needs to set penalty items on interfaces of different subdomains to control solving precision, and the effect of the method is seriously dependent on the selection of penalty factors, so that the complexity and uncertainty of an algorithm are increased. (2) The multi-branch RWG basis function method has the advantages that the construction process of the basis function is extremely complex, the realization difficulty is high, and the calculation cost is high. However, a common limitation of both approaches is that their non-conformal meshes can only appear at the interfaces of pre-partitioned different sub-domains (domains), belonging to local non-conformality. For special structures where the via array is spread over the global in advanced packaging, the simulation area cannot be effectively divided into multiple independent subfields using the area decomposition method, so the existing DDM-based local non-conformal grid technology is no longer applicable to such problems. In this context, a global non-conformal mesh technique that enables free application of non-conformal meshes throughout the simulation area becomes a necessary need. The method provided by the application is the only current resistive-inductive parameter extraction technology capable of supporting the global non-conformal grid, and perfectly solves the grid subdivision problem in the advanced packaging structure simulation. Disclosure of Invention In view of this, the present application provides a method, apparatus, computer device and storage medium for extracting resistive and inductive parameters, and the core matrix of the linear system obtained by the embodiment of the present application can be directly used for rapid algorithm configuration, and simultaneously adapt to the non-conformal grid of the total office. The embodiment of the application discloses a method for extracting resistance inductance parameters, which comprises the following steps: Dividing the surface of the conductor into surface elements, wherein the surface elements are triangle and bilinear surface mixed surface elements; Constructing a sparse mapping matrix from a loop to the bin; Discrete conductor surface currents based on centroid basis functions; Mapping the current of the loop onto the bin based on the sparse mapping matrix; constructing a precondition matrix; accelerating matrix vector multiplication based on the bin configuration FMM algorithm; and (5) post-processing to obtain the resistance inductance parameter. Wherein the mapping the current of the loop onto the bin based on the sparse mapping matrix comprises: And mapping the loop current to the surface element based on the sparse mapping matrix, and extracting the current directivity to the matrix element at one time in the mapping process, so that the vector bit integration of the non-conformal grid is converted into the scalar bit integration of the monopole mode. The second aspect of the embodiment of the application discloses a resistor inductance parameter extraction device, which comprises: the subdivision module is used for subdividing the surface of the conductor into surface elements, wherein the surface elements are triangle and bilinear surface mixed surface elements; a first construction module for constructing a sparse mapping matrix of loops to the bins; A discrete module for dispersing the conductor surface current based on the centroid basic function; a mapping module for mapping the current of the loop onto the bin based on the sparse mapping matrix; The second construction module is used for constructing a precondition matrix; the configuration module