CN-121997515-A - Method, device, equipment and medium for measuring performance reliability of power semiconductor device

CN121997515ACN 121997515 ACN121997515 ACN 121997515ACN-121997515-A

Abstract

The invention provides a method, a device, equipment and a medium for measuring the performance reliability of a power semiconductor device, wherein the method for measuring the performance reliability of the power semiconductor device comprises the steps of performing experimental design based on a uniform design method, and adopting a design table with minimum centralization deviation as the uniform design table; the method comprises the steps of determining a performance response proxy model of a target power semiconductor device according to a least square method, determining an uncertain limit state function of the target power semiconductor device through a stress-intensity interference model, determining an uncertainty measure of the target power semiconductor device according to the uncertain limit state function and a design variable distribution function, obtaining a performance reliability measure model according to the uncertainty measure, and solving the model to obtain a performance reliability measure result of the target power semiconductor device. The method has the beneficial effect that the measurement accuracy of the performance reliability of the power semiconductor device in the forward design stage is improved.

Inventors

RONG ZHILIN
ZHOU SHUANG
LIU WENYE
CHEN YANPING
LIU XINGPING
LI DONGLEI
WANG LIPING
ZHANG DONGHUI
Sun Liuwang

Assignees

中车株洲电力机车研究所有限公司

Dates

Publication Date: 20260508
Application Date: 20241105

Claims (10)

1. A method for measuring performance reliability of a power semiconductor device, comprising: Performing experimental design based on a uniform design method, and generating a plurality of alternative uniform design tables according to the number of design variables and the number of levels; according to the uniformity of the hyper-rectangle measured by the centralization deviation, selecting a design table with the minimum centralization deviation value from the alternative uniform design table as a uniform design table of the target power semiconductor device; Performing physical tests or simulation analysis according to the uniform design table, obtaining design variables and performance response sample values, and determining a performance response proxy model of the target power semiconductor device based on a least square method, wherein the uncertain variables are used for representing the design variables affecting key performance parameters; Determining an uncertain limit state function of the target power semiconductor device through a stress-intensity interference model according to the performance response agent model and the performance response threshold; Determining uncertainty measure of the target power semiconductor device according to the uncertainty limit state function and the design variable distribution function, and obtaining a performance reliability measurement model according to the uncertainty measure; and solving the performance reliability measurement model by adopting an equivalent analytical model calculation method and a numerical simulation calculation method to obtain a performance reliability measurement result of the target power semiconductor device.
2. The method of claim 1, wherein the step of generating a plurality of candidate uniform design tables based on the number of design variables and the number of levels by performing experimental design based on a uniform design method, and the step of selecting a design table having a smallest centralized deviation value as a uniform design table of a target power semiconductor device based on the uniformity of the hyper-rectangle measured by the centralized deviation comprises: Obtaining a uniform design table by adopting a uniform design method, wherein the uniform design table is expressed as U s (s n ) th or third Wherein U represents a uniform design, s represents the number of experiments, n represents the number of input factors, and x represents a design table with smaller deviation and better uniformity; In each experiment, the values of each design variable are not mutually limited, the test area with the values not mutually limited is a super rectangle, and the super rectangle is recorded as Wherein the number of input factors n is equal to the number of design variables; The hyper-rectangle C n is measured by taking the centralization deviation CD as uniformity measure to obtain uniformity, wherein the square value C D 2 of the centralization deviation is Where ζ= (ζ 1 ,ξ 2 ,…,ξ n ) T is the vector of design variables, Is an experimental sample point set ζ i consisting of s tests in C n , i.e. ζ i ＝(ξ ij )∈C n .
3. The method of claim 1, wherein the step of performing a physical test or a simulation analysis according to a uniform design table to obtain design variables and performance response sample values, and determining a performance response proxy model of the target power semiconductor device based on a least square method comprises: Generating experimental sample points of design variables and performance response by adopting multiple physical tests or simulation analysis, taking the design variables of a quadratic polynomial which does not comprise cross terms as uncertain variables, and determining a performance response proxy model of the target power semiconductor device by a uniform design method and a least square method, wherein the performance response proxy model comprises the following steps: Where ζ= (ζ 1 ,ξ 2 ,…,ξ n ) T is a vector of n-dimensional uncertainty random variables, which is determined from the uniform design table sampling, b= (b 0 ,b 1 ,…,b 2n ) T is a vector of 2n+1 coefficients to be determined in the performance response proxy model).
4. A method of measuring performance reliability of a power semiconductor device according to claim 3 wherein said determining an uncertainty limit state function of a target power semiconductor device by a stress-intensity interference model based on said performance response proxy model and a performance response threshold comprises: the uncertain limit state function is constructed according to the stress-intensity interference model as G (ζ): G(ξ)=f(ξ 1 ,ξ 2 ,…,ξ n )＝S threshold -S(ξ 1 ,ξ 2 ,…,ξ n ) Determining b= (a T a) -1 a T y according to the least square method, wherein a is an m× (2n+1) order regression coefficient vector, and y= (g (ζ 1 ),g(ξ 2 ),…,g(ξ m )) T is a vector formed by performance responses corresponding to key performance parameters; Updating the uncertain limit state function according to the least square method and the stress-intensity interference model to obtain: where S threshold is the performance response threshold, A proxy model for performance response.
5. The method of claim 4, wherein determining the uncertainty measure of the target power semiconductor device according to the uncertainty limit state function and the design variable, and obtaining the performance reliability measure model according to the uncertainty measure comprises: acquiring a design variable, and determining the credibility of an event according to the design variable and an uncertain limit state function, wherein the credibility of the event is represented as { G (ζ) >0}; Determining uncertainty measure based on confidence of event Uncertainty space built as triples Wherein Γ is a set comprising events, wherein Is a sigma algebra within Γ, where the uncertainty space satisfies normative, dual, sub-additivity, and product axiom; Performance reliability metric model for obtaining uncertainty measure from uncertainty space The method comprises the following steps:
6. The method for measuring performance reliability of a power semiconductor device according to claim 5, wherein the equivalent analytical model calculation method comprises: The regular uncertainty distribution function is determined by the uncertainty limit state function G (ζ) =f (ζ 1 ,ξ 2 ,…,ξ n ) and the uncertainty variable ζ 1 ,ξ 2 ,…,ξ n as: Φ 1 (ξ 1 ),Φ 2 (ξ 2 ),…,Φ n (ξ n ) If the uncertain limit state function is strictly monotonically increasing for ζ 1 ,ξ 2 ,…,ξ m and strictly monotonically decreasing for ζ m+1 ,ξ m+2 ,…,ξ n , wherein 1< m < n, the target semiconductor failure reliability is: The performance reliability measurement model is determined according to the target semiconductor failure reliability: the equivalent analytical model for determining the performance reliability measurement model according to the limit state function and the uncertain inverse distribution function is as follows: Where α is the root of the equivalent analytical model.
7. The method for measuring performance reliability of a power semiconductor device according to claim 5, the numerical simulation calculation is characterized by comprising the following steps: under the uncertain space, generating a group of uncertain variables xi k by an uncertain inverse distribution function as follows: Wherein, k=1, N; Sequencing the size of the uncertain variable xi k to obtain In the order of k=1 to k=n, m 1 (i)＝m 1 (i) +1 if G (ζ k ) >0, If G (ζ k ) is less than or equal to 0, m 2 (i)＝m 2 (i) +1, If m 1 >0 and m 2 >0, for i=1, 2.., Has the following components If M 1 >0, then m=1, if M 2 >0, then m=0; If A (i) is less than 0.5 If B (i) is less than 0.5 Otherwise Such as M=a, if M=1-B, otherwise m=0.5; Obtaining reliability estimation value of performance reliability measurement model
8. A power semiconductor device performance reliability measurement apparatus, comprising: The first module is used for carrying out experimental design based on a uniform design method and generating a plurality of alternative uniform design tables according to the number of design variables and the number of levels; A second module, configured to measure uniformity of the hyper-rectangle according to the centralized deviation, and select a design table with the smallest centralized deviation value from the alternative uniform design tables as a uniform design table of the target power semiconductor device; The third module is used for carrying out physical test or simulation analysis according to the uniform design table, obtaining design variables and performance response sample values, and determining a performance response proxy model of the target power semiconductor device based on a least square method, wherein the uncertain variables are used for representing the design variables affecting key performance parameters; a fourth module, configured to determine an uncertain limit state function of the target power semiconductor device according to the performance response proxy model and the performance response threshold value through a stress-intensity interference model; A fifth module, configured to determine an uncertainty measure of the target power semiconductor device according to the uncertainty limit state function and the design variable distribution function, and obtain a performance reliability metric model according to the uncertainty measure; And a sixth module, configured to solve the performance reliability measurement model by using an equivalent analytical model calculation method and a numerical simulation calculation method, so as to obtain a performance reliability measurement result of the target power semiconductor device.
9. An electronic device comprising a processor and a memory; the memory is used for storing programs; execution of the program by the processor implements the power semiconductor device performance reliability measurement method of any one of claims 1-7.
10. A computer-readable storage medium, characterized in that the storage medium stores a program that is executed by a processor to implement the power semiconductor device performance reliability measurement method of any one of claims 1 to 7.

Description

Method, device, equipment and medium for measuring performance reliability of power semiconductor device Technical Field The present invention relates to the field of power semiconductor reliability design and evaluation technologies, and in particular, to a method, an apparatus, a device, and a medium for measuring performance reliability of a power semiconductor device. Background Reliability assessment is a key quality characteristic in the forward design process of an IGBT (insulated gate bipolar transistor) power device, and performance reliability assessment needs to consider design variables affecting key performance parameters of a power semiconductor device. In the design stage of the scheme, due to the lack of enough experimental statistical data, sample data of design variables are usually insufficient, and how to accurately quantify reliability under different sample size conditions and guide iterative optimization of product design is a reliability engineering technical problem to be solved urgently at present. Aiming at the reliability analysis of the power semiconductor device, if the design variable sample data are sufficient, the classical probability reliability analysis theory based on mathematical statistics can accurately describe the performance reliability of the product. However, if the design variable sample data is insufficient, especially for the power semiconductor device in the forward design stage, there are a large number of unavoidable factors of cognitive uncertainty (EPISTEMIC UNCERTAINTY) such as material properties, power loss, external load, structural dimensions, and application conditions, and the reliability cannot be accurately measured by probability measurement. Disclosure of Invention The embodiment of the invention mainly aims to provide a method, a device, equipment and a medium for measuring the performance reliability of a power semiconductor device, so that the accuracy of performance evaluation of the power semiconductor device is improved. An aspect of the present invention provides a method for measuring performance reliability of a power semiconductor device, including: Performing experimental design based on a uniform design method, and generating a plurality of alternative uniform design tables according to the number of design variables and the number of levels; According to the uniformity of the hyper-rectangle measured by the centralization deviation, selecting a design table with the minimum centralization deviation value from the alternative design tables as a uniform design table of the target power semiconductor device; performing physical test or simulation analysis according to the uniform design table, obtaining design variables and performance response sample values, and determining a performance response proxy model of the target power semiconductor device based on a least square method, wherein the uncertain variables are used for representing the design variables affecting key performance parameters; Determining an uncertain limit state function of the target power semiconductor device through a stress-intensity interference model according to the performance response agent model and the performance response threshold; Determining uncertainty measure of the target power semiconductor device according to the uncertainty limit state function and the design variable distribution function, and obtaining a performance reliability measurement model according to the uncertainty measure; and solving the performance reliability measurement model by adopting an equivalent analytical model calculation method and a numerical simulation calculation method to obtain a performance reliability measurement result of the target power semiconductor device. According to the method for measuring the performance reliability of the power semiconductor device, experimental design is carried out based on a uniform design method, a plurality of alternative uniform design tables are generated according to the number of design variables and the number of levels, the uniformity of the hyper-rectangle is measured according to the centralized deviation, and the design table with the minimum centralized deviation value is selected as the uniform design table of the target power semiconductor device, and the method comprises the following steps: Obtaining a uniform design table by adopting a uniform design method, wherein the uniform design table is expressed as U s(sn) th or third Wherein U represents a uniform design, s represents the number of experiments, n represents the number of input factors, and x represents a design table with smaller deviation and better uniformity; In each experiment, the values of each design variable are not mutually limited, the test area with the values not mutually limited is a super rectangle, and the super rectangle is recorded as Wherein the number of input factors n is equal to the number of design variables; The hyper-rectangle C n i