CN-121997848-A - SoC reset circuit generation method based on node negotiation

CN121997848ACN 121997848 ACN121997848 ACN 121997848ACN-121997848-A

Abstract

The invention provides a node negotiation-based SoC reset circuit generation method, which comprises the following steps of defining reset node connection information and a reset negotiation rule, obtaining original code information containing the reset node connection information, generating a connection structure of a reset tree according to the reset negotiation rule, and generating a final SoC reset circuit according to the reset node connection structure to complete SoC reset circuit generation based on node negotiation, wherein the reset node connection information is defined in the step 1. The invention improves the design efficiency of the reset circuit generation method, enhances the design flexibility of the reset circuit generation method, improves the code quality of the reset circuit generation method, and reduces the complexity while maintaining intuitiveness.

Inventors

ZHOU SHUAI
WANG GUANTAO
GU GANGWEI
LI YUCONG
CHEN JIEKAI

Assignees

杭州万高科技股份有限公司

Dates

Publication Date: 20260508
Application Date: 20241108

Claims (10)

1. The method for generating the SoC reset circuit based on the node negotiation is characterized by comprising the following steps of: step 1, defining reset node connection information and a reset negotiation rule; step 2, obtaining original code information containing reset node connection information; Step 3, generating a connection structure of a reset tree according to a reset negotiation rule; And step 4, generating a final SoC reset circuit according to the reset node connection structure, and completing the generation of the SoC reset circuit based on node negotiation.
2. The method for generating the SoC reset circuit based on the node negotiation of claim 1, wherein defining the reset node connection information comprises: Reset nodes and connectors are defined.
3. The method for generating the SoC reset circuit based on the node negotiation of claim 2, wherein defining the reset node comprises: A reset node parameter and a reset node type are defined.
4. The method for generating a SoC reset circuit based on node negotiation of claim 3, wherein the reset node parameters include an in-edge parameter and an out-edge parameter.
5. The method of claim 4, wherein the in-edge parameter represents a negotiation result with an upstream reset node, and provides information from the upstream reset node to a current reset node.
6. The method for generating a SoC reset circuit based on node negotiation of claim 4, wherein the out-edge parameter represents a negotiation result with a downstream reset node, and provides information of a current reset node for the downstream reset node.
7. The method of SoC reset circuit generation based on node negotiation of claim 4, wherein the reset node types comprise a reset source node, a reset routing node and a reset destination node, wherein, The reset source node is a starting point in a reset tree and is used for providing an initial reset signal; The reset source node comprises a power-on reset node, a watchdog reset node and an external reset node; the reset source node needs to set the effective level; The reset source node only has an edge outlet parameter, and the edge outlet parameter of the reset source node contains reset information in the reset source node; the reset routing node is an intermediary in a reset tree and is used for distributing and managing reset signals, and comprises reset extension, reset merging and reset synchronization; The reset routing node comprises a reset delay node and a reset synchronous node, and also comprises a self-defined reset routing node; the reset routing node is provided with an in-edge parameter and an out-edge parameter, the in-edge parameter of the reset routing node is the negotiation result of the reset routing node and an upstream reset node, and the out-edge parameter of the reset routing node is the negotiation result of the reset routing node and a downstream reset node; The reset destination node is an ending point in the reset tree and is used for receiving and consuming a reset signal; the reset destination node comprises an IP node, a CPU node, a JTAG node, a UART node and a DSP node; the reset destination node receives a reset signal from an upstream reset node; The reset destination node only has an in-edge parameter, and the in-edge parameter of the reset destination node is a negotiation result with an upstream node.
8. The method for generating the SoC reset circuit based on node negotiation of claim 7, wherein the defining the connector comprises: The connection symbol < - > is used as a connector for indicating the connection direction of the node according to the connection rule and generating an in-edge parameter and an out-edge parameter for each connection.
9. The method for generating the SoC reset circuit based on the node negotiation of claim 8, wherein the connection rule comprises: reset nodes on the left and right sides of the connector are a slave node and a master node respectively; The reset routing nodes allow direct connection; each time the reset node is connected, an in-edge parameter or an out-edge parameter is created for the reset nodes on two sides; The reset source node is a master node relative to the reset route node and the reset destination node, the reset route node is a slave node relative to the reset source node and the reset destination node is a master node relative to the reset destination node, and the reset destination node is a slave node relative to the reset source node and the reset route node.
10. The method for generating a SoC reset circuit based on node negotiation of claim 9, wherein the reset negotiation rule in step 3 comprises: rule 1, judge every source node of reset, and confirm whether it participates in reset extension, reset to merge and reset to synchronize; Rule 2, judge every reset destination node, confirm and influence all reset source nodes of the said reset destination node; rule 3, setting reset active level of reset source node and reset destination node; rule 4, judging whether the reset trigger of the reset destination node is independent; rule 5, judging whether each reset destination node needs reset extension and reset synchronization.

Description

SoC reset circuit generation method based on node negotiation Technical Field The invention relates to a method for generating a SoC reset circuit, in particular to a method for generating a SoC reset circuit based on node negotiation. Background This section provides merely background information related to the present disclosure and is not necessarily prior art. In modern System on Chip (SoC) design flow, reset requirements and architecture thereof often face changes due to variability of IP modules and application scenarios. This poses a challenge in that the chip design engineer needs to update the reset architecture diagram and corresponding code synchronously with each change. The frequent change and synchronous update not only increases the complexity of the design stage, but also increases the possibility of errors, and correspondingly prolongs the research and development period. Although methods exist today that generate reset code based on tables or schematics, these methods typically require engineers to draw each component and the relationships between them in detail, which is not only cumbersome, but also increases the probability of errors to some extent, especially as architecture complexity increases. In order to solve the above technical problems, in the prior art, the invention patent application CN116301775A, which is a code generation method, device and equipment based on a chip reset tree prototype graph, proposes a method based on a reset tree prototype graph, and the method is visual, but the construction of a detailed prototype graph is very time-consuming and error-prone. For complex and large-scale reset networks, even small modifications may require a significant amount of manual adjustment and verification effort. It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art. Disclosure of Invention The invention aims to solve the technical problem of providing a node negotiation-based SoC reset circuit generation method aiming at the defects of the prior art. In order to solve the technical problems, the invention discloses a method for generating a SoC reset circuit based on node negotiation, which comprises the following steps: step 1, defining reset node connection information and a reset negotiation rule; step 2, obtaining original code information containing reset node connection information; Step 3, generating a connection structure of a reset tree according to a reset negotiation rule; And step 4, generating a final SoC reset circuit according to the reset node connection structure, and completing the generation of the SoC reset circuit based on node negotiation. Further, the defining the reset node connection information includes: Reset nodes and connectors are defined. Further, the defining the reset node includes: A reset node parameter and a reset node type are defined. Further, the reset node parameters include an in-edge parameter and an out-edge parameter. Further, the edge entering parameter represents a negotiation result with the upstream reset node, and provides information from the upstream reset node for the current reset node. Further, the edge parameter represents a negotiation result with the downstream reset node, and provides current reset node information for the downstream reset node. Further, the reset node type comprises a reset source node, a reset route node and a reset destination node, wherein, The reset source node is a starting point in a reset tree and is used for providing an initial reset signal; The reset source node comprises a power-on reset node, a watchdog reset node and an external reset node; the reset source node needs to set the effective level; The reset source node only has an edge outlet parameter, and the edge outlet parameter of the reset source node contains reset information in the reset source node; the reset routing node is an intermediary in a reset tree and is used for distributing and managing reset signals, and comprises reset extension, reset merging and reset synchronization; The reset routing node comprises a reset delay node and a reset synchronous node, and also comprises a self-defined reset routing node; the reset routing node is provided with an in-edge parameter and an out-edge parameter, the in-edge parameter of the reset routing node is the negotiation result of the reset routing node and an upstream reset node, and the out-edge parameter of the reset routing node is the negotiation result of the reset routing node and a downstream reset node; The reset destination node is an ending point in the reset tree and is used for receiving and consuming a reset signal; the reset destination node comprises an IP node, a CPU node, a JTAG node, a UART node and a DSP node; the reset destination node receives a r