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CN-121997852-A - Multipath 2711 digital logic simulation architecture system based on Verilog HDL

CN121997852ACN 121997852 ACN121997852 ACN 121997852ACN-121997852-A

Abstract

The invention discloses a multipath 2711 digital logic simulation architecture system based on Verilog HDL, which comprises a demand module, a test case TESTCASE module and a 2711 model 2711_MOD module, wherein the multipath 2711 digital logic simulation architecture based on Verilog HDL is established, the problems that the application scene of the traditional 2711 simulation architecture is single and needs to be continuously modified to be suitable for various application scenes of various projects are solved, the simulation architecture system is suitable for various application scenes of various projects through parameter transmission and analysis, and the simulation verification efficiency of various application scenes of various projects about 2711 is improved. The multipath 2711 digital logic simulation architecture based on Verilog HDL can finish the adaptive modification of requirements on the test case TESTCASE level according to the requirements, and the lower layer 2711 model 2711_MOD does not need to be modified, so that the lower layer 2711 model 2711_MOD has stronger applicability and more flexible application.

Inventors

  • HUANG HANLING

Assignees

  • 北京轩宇信息技术有限公司

Dates

Publication Date
20260508
Application Date
20251217

Claims (10)

  1. 1. The multipath 2711 digital logic simulation architecture system based on Verilog HDL is characterized by comprising a demand module, a test case TESTCASE module and a 2711 model 2711_MOD module; The requirement module is used for providing a data protocol, a frame format, 2711 data rate and case requirement; The test case TESTCASE module is used for setting 2711 data and parameters according to the information provided by the demand module, and transmitting the set 2711 data and parameters to the 2711 model 2711_MOD module; The 2711 model 2711_mod module is used for analyzing the information transferred by the test case TESTCASE module, determining the 2711 data word to be sent and sending the data word according to a set rate, and simultaneously supporting the generation and expansion of multiple paths of independent data.
  2. 2. The Verilog HDL-based multi-channel 2711 digital logic simulation architecture system of claim 1, wherein said test case TESTCASE module includes a 2711 data setting unit and a parameter setting unit; the 2711 data setting unit is configured to set 2711 IDLE code IDLE, length LEN and frame data WORD 0-1023 contents, the IDLE code IDLE is 16 bits, the length LEN is 32 bits, the high 16 bits are test data frame numbers, the low 16 bits are WORD numbers of each frame, 1 WORD corresponds to 2 bytes, and the frame data array capacity is 1024 32 bits; Of the 32 bits of the frame data, the high 12 bits are data word sequence numbers, the bits [19:18] are frame format state identifiers, and the bits [17:16] are used for setting the effective range of 16-bit data; The parameter setting unit is used for performing word setting, and the word setting content comprises frame check setting and frame sequence number setting.
  3. 3. The verilog hdl-based multi-way 2711 digital logic simulation architecture system of claim 2 wherein in the frame format status flag, "01" represents a data error, "11" represents invalid data and the other values represent data correct, the data error comprises a data protocol error involving RKMSB, RKLSB, data start bit, data end bit, data idle code, and an input data frame format error involving a frame sync header, a master header, a data field containing a frame sync header word.
  4. 4. The verilog hdl-based multi-way 2711 digital logic simulation architecture system of claim 2 wherein when bits [17:16] are "11", all 16 bits in the data of the lower 16 bits are K codes, when "01", the upper 8 bits in the data of the lower 16 bits are valid data, the lower 8 bits are K codes, when "10", the upper 8 bits in the data of the lower 16 bits are K codes, the lower 8 bits are valid data, and when "00", all 16 bits in the data of the lower 16 bits are valid data.
  5. 5. The Verilog HDL-based multi-channel 2711 digital logic simulation architecture system of claim 2, wherein said frame check settings include a frame check type, a frame check start and stop word sequence number, a frame check field start and stop word sequence number, and said frame sequence number settings include a frame sequence number field start and stop word sequence number, a frame sequence number field start and stop byte high and low byte, a count step size, and a count start.
  6. 6. The Verilog HDL-based multi-channel 2711 digital logic simulation architecture system of claim 1, wherein said 2711 model 2711_MOD module includes 4 sub-modules each having a word setting unit and a send word unit; the word setting unit is used for realizing frame sequence number setting and frame check setting; The sending word unit is used for determining the symbol rate of the sending word, analyzing the related information and determining the specific content of the sending word data, and generating the sending data word for simulation test.
  7. 7. The Verilog HDL-based multi-channel 2711 digital logic simulation architecture system of claim 6, wherein said frame number setting is accomplished by parsing a 32-bit frame number setting parameter TNUM, of which the upper 12 bits are the frame number field start word number, bits [19:18] are the frame number field start word high and low bytes, bits [17:6] are the frame number field end word number, bits [5:4] are the frame number field end word high and low bytes, bits [3:2] are the count step size, and bits [1:0] are the count start.
  8. 8. The Verilog HDL-based multi-channel 2711 digital logic simulation architecture system of claim 6, wherein said frame check setting is accomplished by parsing 332 bit frame check setting parameters TCHK.about.2, TCHK0 is used to set frame check type, TCHK1 is used to set frame check start and stop word sequence numbers, TCHK2 is used to set frame check field start and stop word sequence numbers.
  9. 9. The Verilog HDL-based multi-channel 2711 digital logic simulation architecture system according to claim 6, wherein said transmit WORD unit parses 2711 IDLE code IDLE, length set LEN and frame data WORD 0-1023 contents, determines transmit WORD data by combining frame check values with frame number field contents, and uses self-generated random data when frame data bits [19:18] are "11".
  10. 10. The Verilog HDL-based multi-channel 2711 digital logic simulation architecture system according to claim 1, wherein the 2711 model 2711_MOD module can generate 4 paths of independent 2711 data simultaneously, n x 4 paths of independent 2711 data can be obtained through multiple call instantiations, and n is the number of call instantiations.

Description

Multipath 2711 digital logic simulation architecture system based on Verilog HDL Technical Field The invention relates to the technical field of simulation test, in particular to a multipath 2711 digital logic simulation architecture system based on Verilog HDL. Background Simulation verification is an essential step of digital logic design test, and is one of effective means for guaranteeing digital logic design quality. The quality of the input data for testing directly influences the testing effect, and a plurality of application scenes such as functions, performances, interface protocols and the like need to be covered in all directions during testing and evaluation, so that the input data is required to have personalized characteristics. For example, the test function needs to cover the data types in all interface protocols to confirm that all input 2711 data can be received and parsed correctly, and the test function needs to specify bits and fields to violate the protocol to confirm that abnormal input data can be processed correctly without affecting the subsequent receiving and parsing of 2711 data. The difficulty level of input data generation for testing directly influences the testing efficiency. The simulation time is not considered, and the test period is mainly distributed in three stages of design understanding before test, environment construction in test and data recording and arrangement after test. The most intuitive way to evaluate the friendliness of the simulation architecture is based on the difficulty level of the input data for testing. The simulation framework capable of generating input data for test through simple setting is more friendly, and a large amount of environment construction time can be saved. The simulation framework can generate input data for normal function test and abnormal input data for interface protocol, and can change data rate, the application range is wider, and the test time of one item and the test time of one type of item are saved. The need for such simulation architectures is even more stringent in the current and anticipated future of testing periods being continually compressed. The existing 2711 simulation architecture has the problem of single application scene, needs to be continuously modified to be suitable for various application scenes of each project, seriously influences the simulation verification efficiency, and cannot meet diversified test requirements, so that a multi-channel 2711 digital logic simulation architecture which can adapt to various application scenes of multiple projects, does not need to be frequently modified and can improve the simulation verification efficiency is needed. Disclosure of Invention The invention aims to provide a multipath 2711 digital logic simulation architecture system based on Verilog HDL, which solves the problems existing in the prior art. In order to achieve the purpose, the invention provides a technical scheme that a multipath 2711 digital logic simulation architecture system based on Verilog HDL comprises a demand module, a test case TESTCASE module and a 2711 model 2711_MOD module; The requirement module is used for providing a data protocol, a frame format, 2711 data rate and case requirement; The test case TESTCASE module is used for setting 2711 data and parameters according to the information provided by the demand module, and transmitting the set 2711 data and parameters to the 2711 model 2711_MOD module; The 2711 model 2711_mod module is used for analyzing the information transferred by the test case TESTCASE module, determining the 2711 data word to be sent and sending the data word according to a set rate, and simultaneously supporting the generation and expansion of multiple paths of independent data. Preferably, the test case TESTCASE module includes a 2711 data setting unit and a parameter setting unit; the 2711 data setting unit is configured to set 2711 IDLE code IDLE, length LEN and frame data WORD 0-1023 contents, the IDLE code IDLE is 16 bits, the length LEN is 32 bits, the high 16 bits are test data frame numbers, the low 16 bits are WORD numbers of each frame, 1 WORD corresponds to 2 bytes, and the frame data array capacity is 1024 32 bits; Of the 32 bits of the frame data, the high 12 bits are data word sequence numbers, the bits [19:18] are frame format state identifiers, and the bits [17:16] are used for setting the effective range of 16-bit data; The parameter setting unit is used for performing word setting, and the word setting content comprises frame check setting and frame sequence number setting. Preferably, in the frame format status identifier, "01" indicates a data error, "11" indicates invalid data, and other values indicate that the data is correct, wherein the data error comprises a data protocol error and an input data frame format error, the data protocol error relates to RKMSB, RKLSB, a data start bit, a data end bit and a data idle code, and the input data fr